Xilinx CPLD Libraries Guide

About Design Elements
FDDSRE
Macro: Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset and Clock Enable
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
FDDSRE is a single dual edge triggered D-type flip-flop with synchronous set (S), synchronous reset (R), and
clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, it overrides all other inputs and
sets the Q output High during the Low-to-High or High-to-Low clock transition. (Set has precedence over Reset.)
When synchronous reset (R) is High and S is Low, output Q is reset Low during the Low-to-High or High-to-Low
clock transition. Data is loaded into the flip-flop when S and R are Low and CE is High during the Low-to-High
and High-to-Low clock transitions. When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Port Descriptions
Inputs Outputs
S R CE D C Q
1 X X X › 1
1 X X X fl 1
0 1 X X › 0
0 1 X X fl 0
0 0 0 X X No Change
0 0 1 1 › 1
0 0 1 0 › 0
0 0 1 1 fl 1
0 0 1 0 fl 0
Design Entry Method
This design element is only for use in schematics.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 351