Xilinx CPLD Libraries Guide

FDDSE
Macro: D Flip-Flop with Clock Enable and Synchronous Set
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
About Design Elements
FDDSE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and synchronous set (S)
inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input
and sets the Q output High during the Low-to-High or High-to-Low clock (C) transition. The data on the D
input is loaded into the flip-flop when S is Low and CE is High during the Low-to-High and High-to-Low
clock (C) transitions.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
S CE D C Q
1 X X › 1
1 X X fl 1
0 0 X X No Change
0 1 1 › 1
0 1 0 › 0
0 1 1 fl 1
0 1 0 fl 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
348 www.xilinx.com ISE 10.1