Xilinx CPLD Libraries Guide

About Design Elements
FDDRSE
Macro: Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set and Clock Enable
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
FDDRSE is a single dual edge triggered D-type flip-flop with synchronous reset (R), synchronous set (S), and
clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and
resets the Q output Low during the Low-to-High or High-to-Low clock transitions. (Reset has precedence over
Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High or
High-to-Low clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and
CE is High during the Low-to-High and High-to-Low clock transitions.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
R S CE D C Q
1 X X X › 0
1 X X X fl 0
0 1 X X › 1
0 1 X X fl 1
0 0 0 X X No Change
0 0 1 1 › 1
0 0 1 0 › 0
0 0 1 1 fl 1
0 0 1 0 fl 0
Design Entry Method
This design element is only for use in schematics.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 345