Xilinx CPLD Libraries Guide

About Design Elements
• For twos-complement operation, ACC4 represents numbers between -8 and +7, inclusive. If an addition
or subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is not
registered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B3 –
B0 for ACC4) and the contents of the register, which allows cascading of ACC4s by connecting OFL of one
stage to CI of the next stage.
Ignore CO in twos-complement operation.
The synchronous reset (R) has priority over all other inputs, and when set to High, causes all outputs to go to
logic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clock
enable (CE) is Low.
This design element is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Input Output
R L CE ADD D C Q
1 x x x x Rising 0
0 1 x x Dn Rising Dn
0 0 1 1 x Rising Q0+Bn+CI
0 0 1 0 x Rising Q0-Bn-CI
0 0 0 x x Rising No Change
Q0: Previous value of Q
Bn: Value of Data input B
CI: Value of input CI
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 25