Xilinx CPLD Libraries Guide

About Design Elements
FDDPE
Primitive: Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and
asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other
inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE
is High on the Low-to-High and High-to-Low clock (C) transitions. When CE is Low, the clock transitions
are ignored.
Logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term)
in the macrocell, provided the logic can be completely implemented using the single p-term available for clock
enable without requiring feedback from another macrocell. Only FDDCE and FDDPE flip-flops primitives may
take advantage of the clock-enable p-term.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Port Descriptions
Inputs Outputs
PRE CE D C Q
1 X X X 1
0 0 X X No Change
0 1 0 › 0
0 1 1 › 1
0 1 0 fl 0
0 1 1 fl 1
Design Entry Method
This design element is only for use in schematics.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 339