Xilinx CPLD Libraries Guide

FDDP
Macro: Dual Edge Triggered D Flip-Flop with Asynchronous Preset
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
About Design Elements
This design element is a single dual edge triggered D-type flip-flop with data (D) and asynchronous preset
(PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets
the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the Low-to-High
and High-to-Low clock (C) transitions.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Port Descriptions
Inputs Outputs
PRE C D Q
1 X X 1
0 › 1 1
0 › 0 0
0 fl 1 1
0 fl 0 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
338 www.xilinx.com ISE 10.1