Xilinx CPLD Libraries Guide

About Design Elements
FDDC
Macro: D Dual Edge Triggered Flip-Flop with Asynchronous Clear
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element is a single dual edge triggered D-type flip-flop with data (D) and asynchronous clear
(CLR) inputs and data output (Q). The asynchronous CLR, when High, overrides all other inputs and sets the
Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low on the Low-to-High
and High-to-Low clock (C) transitions.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Port Descriptions
Inputs Outputs
CLR D C Q
1 X X 0
0 1 › 1
0 1 fl 1
0 0 › 0
0 0 fl 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 333