Xilinx CPLD Libraries Guide

FDD8
Macro: Multiple Dual Edge Triggered D Flip-Flop
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
About Design Elements
This design element is a multiple dual edge triggered D-type flip-flop with data inputs (D) and data outputs (Q).
It is an 8-bit register with a common clock (C). The data on the D inputs is loaded into the flip-flop during the
Low-to-High and High-to-Low clock (C) transitions.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
Dz – D0 C Qz – Q0
0 › 0
1 › 1
0 fl 0
1 fl 1
z = bit-width - 1
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
330 www.xilinx.com ISE 10.1