Xilinx CPLD Libraries Guide

FDD4CE
About Design Elements
Macro: 4-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element is a 4-bit data registers with clock enable and asynchronous clear. When clock enable (CE) is
High and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the corresponding
data outputs (Q) during the Low-to-High and High-to-Low clock (C) transitions. When CLR is High, it overrides
all other inputs and resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR CE Dz – D0 C Qz – Q0
1 X X X 0
0 0 X X No Change
0 1 Dn › Dn
0 1 Dn fl Dn
z = bit-width - 1
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
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