Xilinx CPLD Libraries Guide

FDCPE
Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE),
and asynchronous clear (CLR) inputs. The asynchronous active high PRE sets the Q output High; that active
high CLR resets the output Low and has precedence over the PRE input. Data on the D input is loaded into the
flip-flop when PRE and CLR are Low and CE is High on the Low-to-High clock (C) transition. When CE is Low,
the clock transitions are ignored and the previous value is retained. The FDCPE is generally implemented as a
slice or IOB register within the device.
For CPLD devices, you can simulate power-on by applying a High-level pulse on the PRLD global net. For FPGA
devices, upon power-up, the initial value of this component is specified by the INIT attribute. If a subsequent
GSR (Global Set/Reset) is asserted, the flop is asynchronously set to the INIT value.
Note While this device supports the use of asynchronous set and reset, it is not generally recommended to
be used for in most cases. Use of asynchronous signals pose timing issues within the design that are difficult
to detect and control and also have an adverse affect on logic optimization causing a larger design that can
consume more power than if a synchronous set or reset is used.
Logic Table
Inputs Outputs
CLR PRE CE D C Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Change
0 0 1 D › D
CPLD Libraries Guide
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