Xilinx CPLD Libraries Guide

FDCP
Primitive: D Flip-Flop with Asynchronous Preset and Clear
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR)
inputs, and data output (Q). The asynchronous PRE, when High, sets the (Q) output High; CLR, when High,
resets the output Low. Data on the (D) input is loaded into the flip-flop when PRE and CLR are Low on the
Low-to-High clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR PRE D C Q
1 X X X 0
0 1 X X 1
0 0 D › D
Design Entry Method
This design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT 1-Bit Binary 0 or 1 0 Sets the initial value
of Q output after
configuration
CPLD Libraries Guide
318 www.xilinx.com ISE 10.1