Xilinx CPLD Libraries Guide

FD8
Macro: Multiple D Flip-Flop
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a multiple D-type flip-flops with data inputs (D) and data outputs (Q), with a 8-bit
register, each with a common clock (C). The data on the D inputs is loaded into the flip-flop during the
Low-to-High clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
Dz – D0 C Qz – Q0
0 › 0
1 › 1bit-width - 1
z = bit-width - 1
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
312 www.xilinx.com ISE 10.1