Xilinx CPLD Libraries Guide

FD16RE
Macro: 16-Bit Data Register with Clock Enable and Synchronous Reset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a 16-bit data registers. When the clock enable (CE) input is High, and the synchronous
reset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0)
during the Low-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the data
outputs (Q) Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
R CE Dz – D0 C Qz – Q0
1 X X › 0
0 0 X X No Change
0 1 Dn › Dn
z = bit-width - 1
Design Entry Method
This design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT Binary 16-bit Binary All zeros Sets the initial value
of Q output after
configuration
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
306 www.xilinx.com ISE 10.1