Xilinx CPLD Libraries Guide

D4_16E
Macro: 4- to 16-Line Decoder/Demultiplexer with Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a decoder/demultiplexer. When the enable (E) input of this design element is High, one
of 16 active-High outputs (D15 – D0) is selected with a 4-bit binary address (A3 – A0) input. The non-selected
outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E
input is the data input.
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
302 www.xilinx.com ISE 10.1