Xilinx CPLD Libraries Guide

D2_4E
Macro: 2- to 4-Line Decoder/Demultiplexer with Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a decoder/demultiplexer. When the enable (E) input of this element is High, one of
four active-High outputs (D3 – D0) is selected with a 2-bit binary address (A1 – A0) input. The non-selected
outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E
input is the data input.
Logic Table
Inputs Outputs
A1 A0 E D3 D2 D1 D0
X X 0 0 0 0 0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
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