Xilinx CPLD Libraries Guide

CRD16CE
About Design Elements
Macro: 16-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous
Clear
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element is a dual edge triggered 16-bit cascadable, clearable, binary ripple counter.
The asynchronous clear (CLR), when High, overrides all other inputs and causes the Q outputs to go to logic
level zero. The counter increments when the clock enable input (CE) is High during the High-to-Low and
Low-to-High clock (C) transitions. The counter ignores clock transitions when CE is Low.
Larger counters can be created by connecting the last Q output of the first stage to the clock input of the next
stage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of a
ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the time
tC - Q is the C-to-Qz propagation delay of each stage.
This counter is asynchronously cleared, outputs Low, when power is applied. .For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR CE C Qz – Q0
1 X X 0
0 0 X No Change
0 1 › Inc
0 1 fl Inc
z = bit width - 1
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
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