- Page 1 and 2: ISE 10.1 CPLD Libraries Guide
- Page 3 and 4: Table of Contents About this Guide.
- Page 5 and 6: CDD4CLE ...........................
- Page 7 and 8: FTC................................
- Page 9 and 10: OR5B1..............................
- Page 11: About this Guide This guide is part
- Page 14 and 15: Design Element Description BUFE4 Ma
- Page 16 and 17: Design Element Description Function
- Page 18 and 19: Design Element Description Function
- Page 20 and 21: Design Element Description Function
- Page 22 and 23: Design Element Description OBUFT Pr
- Page 24 and 25: Design Element Description NOR3B2 P
- Page 26 and 27: Design Element Description Function
- Page 30 and 31: ACC1 About Design Elements Macro: 1
- Page 32 and 33: ACC16 About Design Elements Macro:
- Page 34 and 35: ACC4 About Design Elements Macro: 4
- Page 36 and 37: ACC8 About Design Elements Macro: 8
- Page 38 and 39: ADD1 Macro: 1-Bit Full Adder with C
- Page 40 and 41: Design Entry Method This design ele
- Page 42 and 43: Twos-Complement Operation About Des
- Page 44 and 45: Design Entry Method This design ele
- Page 46 and 47: Inputs Outputs A0 B0 CI S0 CO 0 1 1
- Page 48 and 49: About Design Elements With adder/su
- Page 50 and 51: About Design Elements This design e
- Page 52 and 53: Unsigned Binary Operation About Des
- Page 54 and 55: AND2B1 Primitive: 2-Input AND Gate
- Page 56 and 57: AND3 Primitive: 3-Input AND Gate wi
- Page 58 and 59: AND3B2 Primitive: 3-Input AND Gate
- Page 60 and 61: AND4 Primitive: 4-Input AND Gate wi
- Page 62 and 63: AND4B2 Primitive: 4-Input AND Gate
- Page 64 and 65: AND4B4 Primitive: 4-Input AND Gate
- Page 66 and 67: AND5B1 Primitive: 5-Input AND Gate
- Page 68 and 69: AND5B3 Primitive: 5-Input AND Gate
- Page 70 and 71: AND5B5 Primitive: 5-Input AND Gate
- Page 72 and 73: AND7 Macro: 7-Input AND Gate with N
- Page 74 and 75: AND9 Macro: 9-Input AND Gate with N
- Page 76 and 77: BRLSHFT8 Macro: 8-Bit Barrel Shifte
- Page 78 and 79:
BUF Primitive: General Purpose Buff
- Page 80 and 81:
BUF4 Macro: 4-Bit General Purpose B
- Page 82 and 83:
BUFE Primitive: Internal 3-State Bu
- Page 84 and 85:
BUFE4 Macro: 4-BitInternal 3-State
- Page 86 and 87:
BUFG Primitive: Global Clock Buffer
- Page 88 and 89:
BUFGSR Primitive: Global Set/Reset
- Page 90 and 91:
BUFT Primitive: Internal 3-State Bu
- Page 92 and 93:
BUFT4 Macro: 4-Bit Internal 3-State
- Page 94 and 95:
CB16CE Macro: 16-Bit Cascadable Bin
- Page 96 and 97:
CB16CLE About Design Elements Macro
- Page 98 and 99:
CB16CLED About Design Elements Macr
- Page 100 and 101:
CB16RE Macro: 16-Bit Cascadable Bin
- Page 102 and 103:
CB16RLE About Design Elements Macro
- Page 104 and 105:
CB16X1 Macro: 16-Bit Loadable Casca
- Page 106 and 107:
CB16X2 Macro: 16-Bit Loadable Casca
- Page 108 and 109:
CB2CE Macro: 2-Bit Cascadable Binar
- Page 110 and 111:
CB2CLE About Design Elements Macro:
- Page 112 and 113:
CB2CLED Macro: 2-Bit Loadable Casca
- Page 114 and 115:
CB2RE Macro: 2-Bit Cascadable Binar
- Page 116 and 117:
CB2RLE About Design Elements Macro:
- Page 118 and 119:
CB2X1 Macro: 2-Bit Loadable Cascada
- Page 120 and 121:
CB2X2 About Design Elements Macro:
- Page 122 and 123:
CB4CE Macro: 4-Bit Cascadable Binar
- Page 124 and 125:
CB4CLE About Design Elements Macro:
- Page 126 and 127:
CB4CLED Macro: 4-Bit Loadable Casca
- Page 128 and 129:
CB4RE Macro: 4-Bit Cascadable Binar
- Page 130 and 131:
CB4RLE About Design Elements Macro:
- Page 132 and 133:
CB4X1 Macro: 4-Bit Loadable Cascada
- Page 134 and 135:
CB4X2 About Design Elements Macro:
- Page 136 and 137:
CB8CE Macro: 8-Bit Cascadable Binar
- Page 138 and 139:
CB8CLE About Design Elements Macro:
- Page 140 and 141:
CB8CLED Macro: 8-Bit Loadable Casca
- Page 142 and 143:
CB8RE Macro: 8-Bit Cascadable Binar
- Page 144 and 145:
CB8RLE About Design Elements Macro:
- Page 146 and 147:
CB8X1 Macro: 8-Bit Loadable Cascada
- Page 148 and 149:
CB8X2 About Design Elements Macro:
- Page 150 and 151:
CBD16CE About Design Elements Macro
- Page 152 and 153:
CBD16CLE About Design Elements Macr
- Page 154 and 155:
CBD16CLED About Design Elements Mac
- Page 156 and 157:
CBD16RE About Design Elements Macro
- Page 158 and 159:
CBD16RLE About Design Elements Macr
- Page 160 and 161:
CBD16X1 About Design Elements Macro
- Page 162 and 163:
CBD16X2 About Design Elements Macro
- Page 164 and 165:
CBD2CE About Design Elements Macro:
- Page 166 and 167:
CBD2CLE About Design Elements Macro
- Page 168 and 169:
CBD2CLED About Design Elements Macr
- Page 170 and 171:
CBD2RE About Design Elements Macro:
- Page 172 and 173:
CBD2RLE About Design Elements Macro
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CBD2X1 About Design Elements Macro:
- Page 176 and 177:
CBD2X2 About Design Elements Macro:
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CBD4CE About Design Elements Macro:
- Page 180 and 181:
CBD4CLE About Design Elements Macro
- Page 182 and 183:
CBD4CLED About Design Elements Macr
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CBD4RE About Design Elements Macro:
- Page 186 and 187:
CBD4RLE About Design Elements Macro
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CBD4X1 About Design Elements Macro:
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CBD4X2 About Design Elements Macro:
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CBD8CE About Design Elements Macro:
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CBD8CLE About Design Elements Macro
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CBD8CLED About Design Elements Macr
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CBD8RE About Design Elements Macro:
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CBD8RLE About Design Elements Macro
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CBD8X1 About Design Elements Macro:
- Page 204 and 205:
CBD8X2 About Design Elements Macro:
- Page 206 and 207:
CD4CE Macro: 4-Bit Cascadable BCD C
- Page 208 and 209:
CD4CLE About Design Elements Macro:
- Page 210 and 211:
CD4RE Macro: 4-Bit Cascadable BCD C
- Page 212 and 213:
CD4RLE About Design Elements Macro:
- Page 214 and 215:
CDD4CE About Design Elements Macro:
- Page 216 and 217:
CDD4CLE About Design Elements Macro
- Page 218 and 219:
CDD4RE About Design Elements Macro:
- Page 220 and 221:
CDD4RLE About Design Elements Macro
- Page 222 and 223:
CJ4RE Macro: 4-Bit Johnson Counter
- Page 224 and 225:
CJ5RE Macro: 5-Bit Johnson Counter
- Page 226 and 227:
CJ8RE Macro: 8-Bit Johnson Counter
- Page 228 and 229:
CJD4RE About Design Elements Macro:
- Page 230 and 231:
CJD5RE About Design Elements Macro:
- Page 232 and 233:
CJD8RE About Design Elements Macro:
- Page 234 and 235:
CoolRunner-II // Xilinx HDL Languag
- Page 236 and 237:
Verilog Instantiation Template // C
- Page 238 and 239:
CDRST => CDRST, -- Synchronous rese
- Page 240 and 241:
Verilog Instantiation Template // C
- Page 242 and 243:
CoolRunner-II // Xilinx HDL Languag
- Page 244 and 245:
Verilog Instantiation Template // C
- Page 246 and 247:
CDRST => CDRST, -- Synchronous rese
- Page 248 and 249:
Verilog Instantiation Template // C
- Page 250 and 251:
CoolRunner-II // Xilinx HDL Languag
- Page 252 and 253:
Verilog Instantiation Template // C
- Page 254 and 255:
CDRST => CDRST, -- Synchronous rese
- Page 256 and 257:
Verilog Instantiation Template // C
- Page 258 and 259:
Verilog Instantiation Template // C
- Page 260 and 261:
Verilog Instantiation Template // C
- Page 262 and 263:
CDRST => CDRST, -- Synchronous rese
- Page 264 and 265:
Verilog Instantiation Template // C
- Page 266 and 267:
CoolRunner-II // Xilinx HDL Languag
- Page 268 and 269:
Verilog Instantiation Template // C
- Page 270 and 271:
CDRST => CDRST, -- Synchronous rese
- Page 272 and 273:
Verilog Instantiation Template // C
- Page 274 and 275:
CoolRunner-II // Xilinx HDL Languag
- Page 276 and 277:
Verilog Instantiation Template // C
- Page 278 and 279:
CDRST => CDRST, -- Synchronous rese
- Page 280 and 281:
Verilog Instantiation Template // C
- Page 282 and 283:
CoolRunner-II // Xilinx HDL Languag
- Page 284 and 285:
Verilog Instantiation Template // C
- Page 286 and 287:
CDRST => CDRST, -- Synchronous rese
- Page 288 and 289:
Verilog Instantiation Template // C
- Page 290 and 291:
CoolRunner-II // Xilinx HDL Languag
- Page 292 and 293:
Verilog Instantiation Template // C
- Page 294 and 295:
CDRST => CDRST, -- Synchronous rese
- Page 296 and 297:
Verilog Instantiation Template // C
- Page 298 and 299:
COMP2 Macro: 2-Bit Identity Compara
- Page 300 and 301:
COMP8 Macro: 8-Bit Identity Compara
- Page 302 and 303:
COMPM2 Macro: 2-Bit Magnitude Compa
- Page 304 and 305:
COMPM8 Macro: 8-Bit Magnitude Compa
- Page 306 and 307:
CR16CE About Design Elements Macro:
- Page 308 and 309:
CRD16CE About Design Elements Macro
- Page 310 and 311:
D2_4E Macro: 2- to 4-Line Decoder/D
- Page 312 and 313:
D4_16E Macro: 4- to 16-Line Decoder
- Page 314 and 315:
FD16 Macro: Multiple D Flip-Flop Su
- Page 316 and 317:
FD16RE Macro: 16-Bit Data Register
- Page 318 and 319:
FD4CE Macro: 4-Bit Data Register wi
- Page 320 and 321:
FD4RE Macro: 4-Bit Data Register wi
- Page 322 and 323:
FD8 Macro: Multiple D Flip-Flop Sup
- Page 324 and 325:
FD8RE Macro: 8-Bit Data Register wi
- Page 326 and 327:
FDCE Primitive: D Flip-Flop with Cl
- Page 328 and 329:
FDCP Primitive: D Flip-Flop with As
- Page 330 and 331:
FDCPE Primitive: D Flip-Flop with C
- Page 332 and 333:
Clock Enable (posedge clk). // All
- Page 334 and 335:
FDD16 Macro: Multiple Dual Edge Tri
- Page 336 and 337:
FDD16RE About Design Elements Macro
- Page 338 and 339:
FDD4CE About Design Elements Macro:
- Page 340 and 341:
FDD8 Macro: Multiple Dual Edge Trig
- Page 342 and 343:
FDD8RE About Design Elements Macro:
- Page 344 and 345:
FDDCE Primitive: Dual Edge Triggere
- Page 346 and 347:
FDDCP Primitive: Dual Edge Triggere
- Page 348 and 349:
FDDP Macro: Dual Edge Triggered D F
- Page 350 and 351:
For More Information • See the ap
- Page 352 and 353:
FDDRE Macro: Dual Edge Triggered D
- Page 354 and 355:
• See the appropriate CPLD Data S
- Page 356 and 357:
For More Information • See the ap
- Page 358 and 359:
FDDSE Macro: D Flip-Flop with Clock
- Page 360 and 361:
For More Information • See the ap
- Page 362 and 363:
For More Information • See the ap
- Page 364 and 365:
• See the appropriate CPLD Data S
- Page 366 and 367:
For More Information • See the ap
- Page 368 and 369:
FDRE Macro: D Flip-Flop with Clock
- Page 370 and 371:
• See the appropriate CPLD Data S
- Page 372 and 373:
Available Attributes Attribute Type
- Page 374 and 375:
FDSE Macro: D Flip-Flop with Clock
- Page 376 and 377:
FDSR Macro: D Flip-Flop with Synchr
- Page 378 and 379:
FJKC Macro: J-K Flip-Flop with Asyn
- Page 380 and 381:
FJKCP Macro: J-K Flip-Flop with Asy
- Page 382 and 383:
FJKCPE Macro: J-K Flip-Flop with As
- Page 384 and 385:
FJKP Macro: J-K Flip-Flop with Asyn
- Page 386 and 387:
For More Information • See the ap
- Page 388 and 389:
For More Information • See the ap
- Page 390 and 391:
For More Information • See the ap
- Page 392 and 393:
FTCE Macro: Toggle Flip-Flop with C
- Page 394 and 395:
FTCLEX Macro: Toggle/Loadable Flip-
- Page 396 and 397:
FTCPE Macro: Toggle Flip-Flop with
- Page 398 and 399:
Design Entry Method This design ele
- Page 400 and 401:
FTDCLE About Design Elements Macro:
- Page 402 and 403:
FTDCLEX About Design Elements Macro
- Page 404 and 405:
FTDCP Primitive: Dual-Edge Triggere
- Page 406 and 407:
FTDRSLE About Design Elements Macro
- Page 408 and 409:
FTP Macro: Toggle Flip-Flop with As
- Page 410 and 411:
FTPLE Macro: Toggle/Loadable Flip-F
- Page 412 and 413:
FTRSE Macro: Toggle Flip-Flop with
- Page 414 and 415:
Design Entry Method This design ele
- Page 416 and 417:
FTSRLE Macro: Toggle/Loadable Flip-
- Page 418 and 419:
GND Primitive: Ground-Connection Si
- Page 420 and 421:
Available Attributes Attribute Type
- Page 422 and 423:
IBUF16 Macro: 16-Bit Input Buffer S
- Page 424 and 425:
IBUF4 Macro: 4-Bit Input Buffer Sup
- Page 426 and 427:
IBUF8 Macro: 8-Bit Input Buffer Sup
- Page 428 and 429:
INV Primitive: Inverter Supported A
- Page 430 and 431:
INV4 Macro: Four Inverters Supporte
- Page 432 and 433:
IOBUFE Primitive: Bi-Directional Bu
- Page 434 and 435:
KEEPER Primitive: KEEPER Symbol Sup
- Page 436 and 437:
LD Primitive: Transparent Data Latc
- Page 438 and 439:
LD4 Macro: Multiple Transparent Dat
- Page 440 and 441:
LD8 Macro: Multiple Transparent Dat
- Page 442 and 443:
For More Information • See the ap
- Page 444 and 445:
About Design Elements Attribute Typ
- Page 446 and 447:
LDG16 Macro: 16-bit Transparent Dat
- Page 448 and 449:
LDG8 Macro: 8-Bit Transparent Datag
- Page 450 and 451:
For More Information • See the ap
- Page 452 and 453:
About Design Elements Inputs Output
- Page 454 and 455:
M2_1B1 Macro: 2-to-1 Multiplexer wi
- Page 456 and 457:
M2_1E Macro: 2-to-1 Multiplexer wit
- Page 458 and 459:
M8_1E Macro: 8-to-1 Multiplexer wit
- Page 460 and 461:
NAND2 Primitive: 2-Input NAND Gate
- Page 462 and 463:
NAND2B2 Primitive: 2-Input NAND Gat
- Page 464 and 465:
NAND3B1 Primitive: 3-Input NAND Gat
- Page 466 and 467:
NAND3B3 Primitive: 3-Input NAND Gat
- Page 468 and 469:
NAND4B1 Primitive: 4-Input NAND Gat
- Page 470 and 471:
NAND4B3 Primitive: 4-Input NAND Gat
- Page 472 and 473:
NAND5 Primitive: 5-Input NAND Gate
- Page 474 and 475:
NAND5B2 Primitive: 5-Input NAND Gat
- Page 476 and 477:
NAND5B4 Primitive: 5-Input NAND Gat
- Page 478 and 479:
NAND6 Macro: 6-Input NAND Gate with
- Page 480 and 481:
NAND8 Macro: 8-Input NAND Gate with
- Page 482 and 483:
NOR2 Primitive: 2-Input NOR Gate wi
- Page 484 and 485:
NOR2B2 Primitive: 2-Input NOR Gate
- Page 486 and 487:
NOR3B1 Primitive: 3-Input NOR Gate
- Page 488 and 489:
NOR3B3 Primitive: 3-Input NOR Gate
- Page 490 and 491:
NOR4B1 Primitive: 4-Input NOR Gate
- Page 492 and 493:
NOR4B3 Primitive: 4-Input NOR Gate
- Page 494 and 495:
NOR5 Primitive: 5-Input NOR Gate wi
- Page 496 and 497:
NOR5B2 Primitive: 5-Input NOR Gate
- Page 498 and 499:
NOR5B4 Primitive: 5-Input NOR Gate
- Page 500 and 501:
NOR6 Macro: 6-Input NOR Gate with N
- Page 502 and 503:
NOR8 Macro: 8-Input NOR Gate with N
- Page 504 and 505:
OBUF Primitive: Output Buffer Suppo
- Page 506 and 507:
OBUF16 Macro: 16-Bit Output Buffer
- Page 508 and 509:
OBUF4 Macro: 4-Bit Output Buffer Su
- Page 510 and 511:
OBUF8 Macro: 8-Bit Output Buffer Su
- Page 512 and 513:
OBUFE Macro: 3-State Output Buffer
- Page 514 and 515:
OBUFE4 Macro: 4-Bit 3-State Output
- Page 516 and 517:
OBUFT Primitive: 3-State Output Buf
- Page 518 and 519:
OBUFT16 Macro: 16-Bit 3-State Outpu
- Page 520 and 521:
OBUFT4 Macro: 4-Bit 3-State Output
- Page 522 and 523:
OBUFT8 Macro: 8-Bit 3-State Output
- Page 524 and 525:
OR2 Primitive: 2-Input OR Gate with
- Page 526 and 527:
OR2B2 Primitive: 2-Input OR Gate wi
- Page 528 and 529:
OR3B1 Primitive: 3-Input OR Gate wi
- Page 530 and 531:
OR3B3 Primitive: 3-Input OR Gate wi
- Page 532 and 533:
OR4B1 Primitive: 4-Input OR Gate wi
- Page 534 and 535:
OR4B3 Primitive: 4-Input OR Gate wi
- Page 536 and 537:
OR5 Primitive: 5-Input OR Gate with
- Page 538 and 539:
OR5B2 Primitive: 5-Input OR Gate wi
- Page 540 and 541:
OR5B4 Primitive: 5-Input OR Gate wi
- Page 542 and 543:
OR6 Macro: 6-Input OR Gate with Non
- Page 544 and 545:
OR8 Macro: 8-Input OR Gate with Non
- Page 546 and 547:
PULLDOWN Primitive: Resistor to GND
- Page 548 and 549:
PULLUP Primitive: Resistor to VCC f
- Page 550 and 551:
SR16CE About Design Elements Macro:
- Page 552 and 553:
SR16CLE About Design Elements Macro
- Page 554 and 555:
SR16CLED Macro: 16-Bit Shift Regist
- Page 556 and 557:
SR16RE About Design Elements Macro:
- Page 558 and 559:
SR16RLE About Design Elements Macro
- Page 560 and 561:
SR16RLED Macro: 16-Bit Shift Regist
- Page 562 and 563:
SR4CE About Design Elements Macro:
- Page 564 and 565:
SR4CLE About Design Elements Macro:
- Page 566 and 567:
SR4CLED Macro: 4-Bit Shift Register
- Page 568 and 569:
SR4RE About Design Elements Macro:
- Page 570 and 571:
SR4RLE About Design Elements Macro:
- Page 572 and 573:
SR4RLED Macro: 4-Bit Shift Register
- Page 574 and 575:
SR8CE About Design Elements Macro:
- Page 576 and 577:
SR8CLE About Design Elements Macro:
- Page 578 and 579:
SR8CLED Macro: 8-Bit Shift Register
- Page 580 and 581:
SR8RE About Design Elements Macro:
- Page 582 and 583:
SR8RLE About Design Elements Macro:
- Page 584 and 585:
SR8RLED Macro: 8-Bit Shift Register
- Page 586 and 587:
SRD16CE About Design Elements Macro
- Page 588 and 589:
SRD16CLE About Design Elements Macr
- Page 590 and 591:
SRD16CLED About Design Elements Mac
- Page 592 and 593:
SRD16RE About Design Elements Macro
- Page 594 and 595:
SRD16RLE About Design Elements Macr
- Page 596 and 597:
SRD16RLED About Design Elements Mac
- Page 598 and 599:
SRD4CE About Design Elements Macro:
- Page 600 and 601:
SRD4CLE About Design Elements Macro
- Page 602 and 603:
SRD4CLED About Design Elements Macr
- Page 604 and 605:
SRD4RE About Design Elements Macro:
- Page 606 and 607:
SRD4RLE About Design Elements Macro
- Page 608 and 609:
SRD4RLED About Design Elements Macr
- Page 610 and 611:
SRD8CE About Design Elements Macro:
- Page 612 and 613:
SRD8CLE About Design Elements Macro
- Page 614 and 615:
SRD8CLED About Design Elements Macr
- Page 616 and 617:
SRD8RE About Design Elements Macro:
- Page 618 and 619:
SRD8RLE About Design Elements Macro
- Page 620 and 621:
SRD8RLED About Design Elements Macr
- Page 622 and 623:
VCC Primitive: VCC-Connection Signa
- Page 624 and 625:
XNOR3 Primitive: 3-Input XNOR Gate
- Page 626 and 627:
XNOR5 Primitive: 5-Input XNOR Gate
- Page 628 and 629:
XNOR7 Macro: 7-Input XNOR Gate with
- Page 630 and 631:
XNOR9 Macro: 9-Input XNOR Gate with
- Page 632 and 633:
XOR3 Primitive: 3-Input XOR Gate wi
- Page 634 and 635:
XOR5 Primitive: 5-Input XOR Gate wi
- Page 636 and 637:
XOR7 Macro: 7-Input XOR Gate with N
- Page 638:
XOR9 Macro: 9-Input XOR Gate with N