Xilinx CPLD Libraries Guide

Verilog Instantiation Template
// CLK_DIV4R: Clock Divide by 4 with Synchronous Reset
// CoolRunner-II
// Xilinx HDL Language Template, version 10.1
CLK_DIV4R CLK_DIV4R_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
// End of CLK_DIV4R_inst instantiation
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
About Design Elements
CPLD Libraries Guide
266 www.xilinx.com ISE 10.1