Xilinx CPLD Libraries Guide

About Design Elements
CLK_DIV2SD
Primitive: Global Clock Divide by 2 with Start Delay
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element divides a user-provided external clock signal gclk by 2.
Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256,
XC2C384, and XC2C512 CoolRunner-IIdevices, but not the XC2C32 or XC2C64. The CLKIN input can only
be connected to the device gclk pin. The duty cycle of the CLKDV output is 50-50. The CLKDV output can
only connect to clock inputs of synchronous elements. It cannot be used as combinatorial logic, and should
not be routed directly to an output pin.
The start delay function delays the start of the CLKDV output by (n + 1) clocks, where n is the divisor for
the clock divider.
The CLKDV output is reset low by power-on reset circuitry.
Design Entry Method
Instantiation Recommended
Inference No
Coregen and wizards No
Macro support No
This design element can be used in schematics.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- CLK_DIV2SD: Clock Divide by 2 with Start Delay
-- CoolRunner-II
-- Xilinx HDL Language Template, version 10.1
CLK_DIV2SD_inst : CLK_DIV2SD
-- Edit the following generic to specify the number of clock cycles
-- to delay before starting.
generic map (
DIVIDER_DELAY => 1)
port map (
CLKDV => CLKDV, -- Divided clock output
CLKIN => CLKIN -- Clock input
);
-- End of CLK_DIV2SD_inst instantiation
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 261