Xilinx CPLD Libraries Guide

Verilog Instantiation Template
// CLK_DIV2R: Clock Divide by 2 with Synchronous Reset
// CoolRunner-II
// Xilinx HDL Language Template, version 10.1
CLK_DIV2R CLK_DIV2R_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
// End of CLK_DIV2R_inst instantiation
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
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CPLD Libraries Guide
258 www.xilinx.com ISE 10.1