Xilinx CPLD Libraries Guide

Verilog Instantiation Template
// CLK_DIV16SD: Clock Divide by 16 with Start Delay
// CoolRunner-II
// Xilinx HDL Language Template, version 10.1
CLK_DIV16SD CLK_DIV16SD_inst (
.CLKDV(CLKDV), // Divided clock output
.CDRST(CDRST), // Synchronous reset input
.CLKIN(CLKIN) // Clock input
);
// Edit the following defparam to specify the number of clock
// cycles to delay before starting. If the instance name to
// the clock divider is changed, that change needs to be
// reflected in the defparam statements.
defparam CLK_DIV16SD_inst.DIVIDER_DELAY = 1;
// End of CLK_DIV16SD_inst instantiation
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
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CPLD Libraries Guide
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