Xilinx CPLD Libraries Guide

About Design Elements
CLK_DIV16R
Primitive: Global Clock Divide by 16 with Synchronous Reset
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element divides a user-provided external clock signal gclk by 16.
Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256,
XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN and CDRST inputs
can only be connected to the device gclk and CDRST pins. The duty cycle of the CLKDV output is 50-50. The
CLKDV output can only connect to clock inputs of synchronous elements. It cannot be used as combinatorial
logic, and should not be routed directly to an output pin.
The CDRST input is an active High synchronous reset. If CDRST is input High when the CLKDV output is High,
the CLKDV output remains High to complete the last clock pulse, and then goes Low.
The CLKDV output is reset low by power-on reset circuitry.
Design Entry Method
Instantiation Recommended
Inference No
Coregen and wizards No
Macro support No
This design element can be used in schematics.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- CLK_DIV16R: Clock Divide by 16 with Synchronous Reset
-- CoolRunner-II
-- Xilinx HDL Language Template, version 10.1
CLK_DIV16R_inst : CLK_DIV16R
port map (
CLKDV => CLKDV, -- Divided clock output
CDRST => CDRST, -- Synchronous reset input
CLKIN => CLKIN -- Clock input
);
-- End of CLK_DIV16R_inst instantiation
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 249