Xilinx CPLD Libraries Guide

CJD5RE
About Design Elements
Macro: 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element is a resettable dual edge triggered Johnson/shift counter. The synchronous reset (R) input,
when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero during the
Low-to-High and High-to-Low clock (C) transitions. The counter increments (shifts Q0 to Q1, Q1 to Q2, etc.)
when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. Clock
transitions are ignored when CE is Low.
The Q4 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. .For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
R CE C Q0 Q1 – Q4
1 X › 0 0
1 X fl 0 0
0 0 X No Change No Change
0 1 › !q4 q0 – q3
0 1 fl !q4 q0 – q3
q = state of referenced output one setup time prior to active clock transition
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
220 www.xilinx.com ISE 10.1