Xilinx CPLD Libraries Guide

About Design Elements
CJD4CE
Macro: 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This element is a dual edge triggered clearable Johnson/shift counter. The asynchronous clear (CLR) input, when
High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero independent of clock (C)
transitions. The counter increments (shifts Q0 to Q1, Q1 to Q2,etc.) when the clock enable input (CE) is High
during the Low-to-High and High-to-Low clock transition. Clock transitions are ignored when CE is Low.
The Q3 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. .For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR CE C Q0 Q1 through Q3
1 X X 0 0
0 0 X No Change No Change
0 1 › !q3 q0 through q2
0 1 fl !q3 q0 through q2
q = state of referenced output one setup time prior to active clock transition
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 217