Xilinx CPLD Libraries Guide

CJ4RE
Macro: 4-Bit Johnson Counter with Clock Enable and Synchronous Reset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a resettable Johnson/shift counter. The synchronous reset (R) input, when High, overrides
all other inputs and forces the data (Q) outputs to logic level zero during the Low-to-High clock (C) transition.
The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High during
the Low-to-High clock transition. Clock transitions are ignored when CE is Low.
The Q3 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. .
Logic Table
Inputs Outputs
R CE C Q0 Q1 through Q3
1 X › 0 0
0 0 X No change No change
0 1 › !q3 q0 through q2
q = state of referenced output one setup time prior to active clock transition
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
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