Xilinx CPLD Libraries Guide

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CDD4CLE About Design Elements Macro: 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear Supported Architectures This design element is supported in the following architectures only: CoolRunner-II Introduction CDD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, dual edge triggered Binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High and High-to-Low clock (C) transitions. The Q outputs increment when clock enable input (CE) is High during the Low- to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Xilinx® devices, as shown in the following state diagram: Create larger counters by connecting the CEO output of each stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input or use the TC output if it does not. CPLD Libraries Guide 206 www.xilinx.com ISE 10.1
About Design Elements This counter is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate power-on by applying a High-level pulse on the PRLD global net. Logic Table Inputs Outputs CLR L CE D3 – D0 C Q3 Q2 Q1 Q0 TC CEO 1 X X X X 0 0 0 0 0 0 0 1 X D3 – D0 › D3 D2 D1 D0 TC CEO 0 1 X D3 – D0 fl D3 D2 D1 D0 TC CEO 0 0 1 X › Inc Inc Inc Inc TC CEO 0 0 1 X fl Inc Inc Inc Inc TC CEO 0 0 0 X X No Change No Change No Change No Change TC 0 0 0 1 X X 1 0 0 1 1 1 TC = Q3•!Q2•!Q1•Q0 CEO = TC•CE Design Entry Method This design element is only for use in schematics. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 207
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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CDD4CLE ...........................
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Design Element Description BUFE4 Ma
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Design Element Description Function
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