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Xilinx CPLD Libraries Guide

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About Design Elements<br />

Logic Table<br />

Inputs Outputs<br />

CLR CE C Q3 Q2 Q1 Q0 TC CEO<br />

1 X X 0 0 0 0 0 0<br />

0 1 › Inc Inc Inc Inc TC CEO<br />

0 0 X No Change No Change No Change No Change TC 0<br />

0 1 X 1 0 0 1 1 1<br />

TC = Q3•!Q2•!Q1•Q0<br />

CEO = TC•CE<br />

Design Entry Method<br />

This design element is only for use in schematics.<br />

For More Information<br />

• See the appropriate <strong>CPLD</strong> User <strong>Guide</strong>.<br />

• See the appropriate <strong>CPLD</strong> Data Sheets.<br />

<strong>CPLD</strong> <strong>Libraries</strong> <strong>Guide</strong><br />

ISE 10.1 www.xilinx.com 197

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