Xilinx CPLD Libraries Guide

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Design Element Description Functional Categories CDD4CE Macro: 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear CDD4CLE Macro: 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear CDD4RE Macro: 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset CDD4RLE Macro: 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset CJ4CE Macro: 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear CJ4RE Macro: 4-Bit Johnson Counter with Clock Enable and Synchronous Reset CJ5CE Macro: 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear CJ5RE Macro: 5-Bit Johnson Counter with Clock Enable and Synchronous Reset CJ8CE Macro: 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear CJ8RE Macro: 8-Bit Johnson Counter with Clock Enable and Synchronous Reset CJD4CE Macro: 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear CJD4RE Macro: 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset CJD5CE Macro: 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear CJD5RE Macro: 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset CJD8CE Macro: 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear CJD8RE Macro: 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset CR16CE Macro: 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear CR8CE Macro: 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear CRD16CE Macro: 16-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear CRD8CE Macro: 8-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear Decoder Design Element Description D2_4E Macro: 2- to 4-Line Decoder/Demultiplexer with Enable D3_8E Macro: 3- to 8-Line Decoder/Demultiplexer with Enable D4_16E Macro: 4- to 16-Line Decoder/Demultiplexer with Enable CPLD Libraries Guide 8 www.xilinx.com ISE 10.1
Functional Categories Flip Flop Design Element Description FD Macro: D Flip-Flop FD16 Macro: Multiple D Flip-Flop FD16CE Macro: 16-Bit Data Register with Clock Enable and Asynchronous Clear FD16RE Macro: 16-Bit Data Register with Clock Enable and Synchronous Reset FD4 Macro: Multiple D Flip-Flop FD4CE Macro: 4-Bit Data Register with Clock Enable and Asynchronous Clear FD4RE Macro: 4-Bit Data Register with Clock Enable and Synchronous Reset FD8 Macro: Multiple D Flip-Flop FD8CE Macro: 8-Bit Data Register with Clock Enable and Asynchronous Clear FD8RE Macro: 8-Bit Data Register with Clock Enable and Synchronous Reset FDC Macro: D Flip-Flop with Asynchronous Clear FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear FDCP Primitive: D Flip-Flop with Asynchronous Preset and Clear FDCPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset and Clear FDD Macro: Dual Edge Triggered D Flip-Flop FDD16 Macro: Multiple Dual Edge Triggered D Flip-Flop FDD16CE Macro: 16-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear FDD16RE Macro: 16-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset FDD4 Macro: Multiple Dual Edge Triggered D Flip-Flop FDD4CE Macro: 4-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear FDD4RE Macro: 4-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset FDD8 Macro: Multiple Dual Edge Triggered D Flip-Flop FDD8CE Macro: 8-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear FDD8RE Macro: 8-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset FDDC Macro: D Dual Edge Triggered Flip-Flop with Asynchronous Clear FDDCE Primitive: Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear FDDCP Primitive: Dual Edge Triggered D Flip-Flop Asynchronous Preset and Clear FDDCPE Macro: Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset and Clear FDDP Macro: Dual Edge Triggered D Flip-Flop with Asynchronous Preset FDDPE Primitive: Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset FDDR Macro: Dual Edge Triggered D Flip-Flop with Synchronous Reset CPLD Libraries Guide ISE 10.1 www.xilinx.com 9
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Page 3 and 4: Table of Contents About this Guide.
Page 5 and 6: CDD4CLE ...........................
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Page 14 and 15: Design Element Description BUFE4 Ma
Page 16 and 17: Design Element Description Function
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Page 24 and 25: Design Element Description NOR3B2 P
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Page 39 and 40: About Design Elements ADD16 Macro:
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About Design Elements AND5B4 Primit
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About Design Elements AND6 Macro: 6
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About Design Elements AND8 Macro: 8
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About Design Elements BRLSHFT4 Macr
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About Design Elements For More Info
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About Design Elements BUF16 Macro:
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About Design Elements BUFE16 Macro:
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About Design Elements BUFE8 Macro:
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About Design Elements BUFG BUFG_ins
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About Design Elements BUFGTS Primit
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About Design Elements BUFT16 Macro:
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About Design Elements Design Entry
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About Design Elements Inputs Output
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About Design Elements D3_8E Macro:
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About Design Elements FD Macro: D F
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About Design Elements FDC Macro: D
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About Design Elements VHDL Instanti
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About Design Elements Port Descript
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About Design Elements FDD Macro: Du
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About Design Elements FDD16CE Macro
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About Design Elements FDDC Macro: D
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About Design Elements FDDCPE Macro:
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About Design Elements FDDPE Primiti
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About Design Elements FDDR Macro: D
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About Design Elements FDDSRE Macro:
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About Design Elements FDP Macro: D
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About Design Elements FDPE Primitiv
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About Design Elements FDR Macro: D
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About Design Elements FTC Primitive
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About Design Elements IBUF Primitiv
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About Design Elements Note Consult
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About Design Elements Attribute Typ
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About Design Elements Note Consult
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About Design Elements Verilog Insta
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About Design Elements LD16 Macro: M
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About Design Elements LDC Macro: Tr
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About Design Elements LDCP Primitiv
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About Design Elements LDG Primitive
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About Design Elements LDG4 Macro: 4
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About Design Elements LDP Macro: Tr
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About Design Elements M16_1E Macro:
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About Design Elements Available Att
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About Design Elements OR2B1 Primiti
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About Design Elements OR7 Macro: 7-
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