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Xilinx CPLD Libraries Guide

Xilinx CPLD Libraries Guide

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Design Element Description<br />

Functional Categories<br />

CDD4CE Macro: 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and<br />

Asynchronous Clear<br />

CDD4CLE Macro: 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock<br />

Enable and Asynchronous Clear<br />

CDD4RE Macro: 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and<br />

Synchronous Reset<br />

CDD4RLE Macro: 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock<br />

Enable and Synchronous Reset<br />

CJ4CE Macro: 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear<br />

CJ4RE Macro: 4-Bit Johnson Counter with Clock Enable and Synchronous Reset<br />

CJ5CE Macro: 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear<br />

CJ5RE Macro: 5-Bit Johnson Counter with Clock Enable and Synchronous Reset<br />

CJ8CE Macro: 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear<br />

CJ8RE Macro: 8-Bit Johnson Counter with Clock Enable and Synchronous Reset<br />

CJD4CE Macro: 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and<br />

Asynchronous Clear<br />

CJD4RE Macro: 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and<br />

Synchronous Reset<br />

CJD5CE Macro: 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and<br />

Asynchronous Clear<br />

CJD5RE Macro: 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and<br />

Synchronous Reset<br />

CJD8CE Macro: 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and<br />

Asynchronous Clear<br />

CJD8RE Macro: 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and<br />

Synchronous Reset<br />

CR16CE Macro: 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and<br />

Asynchronous Clear<br />

CR8CE Macro: 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable and<br />

Asynchronous Clear<br />

CRD16CE Macro: 16-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and<br />

Asynchronous Clear<br />

CRD8CE Macro: 8-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and<br />

Asynchronous Clear<br />

Decoder<br />

Design Element Description<br />

D2_4E Macro: 2- to 4-Line Decoder/Demultiplexer with Enable<br />

D3_8E Macro: 3- to 8-Line Decoder/Demultiplexer with Enable<br />

D4_16E Macro: 4- to 16-Line Decoder/Demultiplexer with Enable<br />

<strong>CPLD</strong> <strong>Libraries</strong> <strong>Guide</strong><br />

8 www.xilinx.com ISE 10.1

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