Xilinx CPLD Libraries Guide

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CBD2X1 About Design Elements Macro: 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear Supported Architectures This design element is supported in the following architectures only: CoolRunner-II Introduction This design element is a synchronously loadable, asynchronously clearable, bidirectional dual edge triggered binary counters. It has separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support high speed cascading. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU and CEOD go to Low and High, respectively, independent of clock transitions. The data on the D inputs loads into the counter on the Low-to-High and High-to-Low clock (C) transition when the load enable input (L) is High, independent of the CE inputs. The Q outputs increment when CEU is High, provided CLR and L are Low, during the Low-to-High and High-to-Low clock transition. The Q outputs decrement when CED is High, provided CLR and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are connected directly to the CEU and CED inputs, respectively, of the next stage. The clock, L, and CLR inputs are connected in parallel. The maximum clocking frequency of these counters is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. This counter is asynchronously cleared, outputs Low, when power is applied. .For CPLD devices, you can simulate power-on by applying a High-level pulse on the PRLD global net. CPLD Libraries Guide 164 www.xilinx.com ISE 10.1
About Design Elements Logic Table Inputs Outputs CLR L CEU CED C Dz–D0 Qz–Q0 TCU TCD CEOU CEOD 1 X X X X X 0 0 1 0 CEOD 0 1 X X › Dn Dn TCU TCD CEOU CEOD 0 1 X X fl Dn Dn TCU TCD CEOU CEOD 0 0 0 0 X X No Change No Change No Change 0 0 0 0 1 0 › X Inc TCU TCD CEOU 0 0 0 1 0 fl X Inc TCU TCD CEOU 0 0 0 0 1 › X Dec TCU TCD 0 CEOD 0 0 0 1 fl X Dec TCU TCD 0 CEOD 0 0 1 1 › X Inc TCU TCD Invalid Invalid 0 0 1 1 fl X Inc TCU TCD Invalid Invalid z = bit width - 1 TCU = Qz•Q(z-1)•Q(z-2)•...•Q0 TCD = Qz•Q(z-1)•Q(z-2)•...•Q0 CEOU = TCU•CEU CEOD = TCD•CED Design Entry Method This design element is only for use in schematics. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 165
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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About this Guide This guide is part
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Design Element Description BUFE4 Ma
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Design Element Description Function
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About Design Elements For More Info
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About Design Elements B0 for ACC16)
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About Design Elements • For twos-
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About Design Elements B0 for ACC8)
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About Design Elements ADD16 Macro:
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About Design Elements Design Entry
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About Design Elements Logic Table I
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About Design Elements The counter i
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About Design Elements CLK_DIV10 Pri
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