III. Gm-C Filtering - Epublications - Université de Limoges
III. Gm-C Filtering - Epublications - Université de Limoges
III. Gm-C Filtering - Epublications - Université de Limoges
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IV.3.a.iii Interests of a BiCMOS Technology<br />
A BiCMOS technology is able to offer a higher transconductance in the differential<br />
pair stage for a same current, as well as a high voltage gain, due to a higher gm/I than in<br />
CMOS technologies. Hence, it may be possible to obtain the required 30dB voltage gain using<br />
a simple OA topology.<br />
Another interest in using NXP BiCMOS technology relies in the possibility to use<br />
MIM (Metal-Insulator-Metal) capacitors. These capacitors, which use metal levels 5 and 6<br />
separated by a high-κ material, exhibit several advantages such as a high Q-factor and a good<br />
linearity. This is very interesting to obtain high quality capacitors banks which do not <strong>de</strong>gra<strong>de</strong><br />
or limit the linearity of the filter. In<strong>de</strong>ed, the 65nm TSMC CMOS technology available at<br />
NXP only allows the use of MOS capacitors characterized by a very high <strong>de</strong>nsity of<br />
integration but also a higher sensitivity to bias and process variations.<br />
IV.3.b Operational Amplifier Design in 0.25µm BiCMOS<br />
IV.3.b.i Initial Design<br />
OA <strong>de</strong>sign in BiCMOS is also based on a two stages topology, as <strong>de</strong>picted in Figure<br />
154. As said, a high gain-bandwidth product is required, as well as a high linearity level.<br />
Current in the differential pair is set to 5mA. For the initial OA <strong>de</strong>sign, the follower is built by<br />
means of a single transistor.<br />
It is worth adding that for <strong>de</strong>coupling, only one Cdc capacitor connected to Vin- is<br />
required since Cf, located in the feedback, also acts as a <strong>de</strong>coupling capacitor for Vin+.<br />
Vin+<br />
Vmirror<br />
T3<br />
T1<br />
Rlp<br />
VDD<br />
bias bias<br />
Clp<br />
T0<br />
5mA<br />
T4<br />
T2<br />
- 138 -<br />
Cdc<br />
Vin-<br />
VDD<br />
Figure 154. Initial schematic of the OA in BiCMOS<br />
Cc<br />
T5<br />
T6<br />
If<br />
Vout