III. Gm-C Filtering - Epublications - Université de Limoges

IV.3 Choice of the Technology and Design of the Rauch Filter
IV.3.a Operational Amplifier Design in 65nm CMOS
IV.3.a.i Possible OA Designs and Performances
To design the specified operational amplifier using a 65nm CMOS technology, a two
stage topology has been chosen. It consists in a differential pair (T1-T2) with an active load
(T3-T4) to create high gain, and an output follower (T5) to provide low output impedance, as
illustrated in Figure 152.
T3
Vin+ Vin- Vout
T1
Vmirror
VDD
bias bias
T0
T4
T2
Figure 152. Schematic of the OA in CMOS
The use of 5mA in the differential pair with 250µm/0.28µm T1 and T2 gives
gm=22.5mS. This poor transconductance leads to a limited OA voltage gain of 15dB as
depicted in Figure 153. Cascode topologies allow increasing the voltage gain but not reaching
the specifications, as illustrated in Figure 153.
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Cc
T5
T6
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