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pSOSystem System Calls - Read

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i_return pSOS+ <strong>System</strong> <strong>Calls</strong><br />

960<br />

x86<br />

SH<br />

On 960 processors, an ISR must restore all global CPU registers,<br />

including the frame pointer, to their state prior to the interrupt. Below is a<br />

sample code fragment for an ISR that internally uses CPU registers g8,<br />

g9, g10, and g11.<br />

movq g8,r8<br />

<br />

movq r8,g8<br />

calls 13<br />

ret<br />

On x86 processors, an ISR must restore all CPU registers to their state<br />

prior to the interrupt. Below is a sample code fragment for an ISR that<br />

internally uses CPU registers ES, EAX, ECX, and EDX.<br />

INT 92H ;PERFORM I_ENTER<br />

PUSH DS ;SAVE SOME REGISTERS<br />

PUSH ES<br />

PUSH EAX<br />

PUSH ECX<br />

PUSH EDX<br />

;HANDLE THE ISR<br />

POP EDX ;RESTORE REGISTERS<br />

POP ECX<br />

POP EAX<br />

POP ES<br />

POP DS<br />

INT 93H ;PERFORM RETURN<br />

On Super Hitachi processors, an ISR must restore all CPU registers,<br />

including the stack pointer, to their state prior to the interrupt. Below is a<br />

sample code fragment for an ISR that internally uses CPU registers r0, r1,<br />

r2, and r3.<br />

mov.l r3, @-sp<br />

mov.l r2, @-sp<br />

mov.l r1, @-sp<br />

mov.l r0, @-sp<br />

<br />

mov.l @sp+, r0<br />

mov.l @sp+, r1<br />

mov.l @sp+, r2<br />

mov.l @sp+, r3<br />

trapa #45<br />

1-38 <strong>pSO<strong>System</strong></strong> <strong>System</strong> <strong>Calls</strong>

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