Threads in the new ISO C Standard from 2011

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Load Load relaxed ld Load consume ld Load acquire ld; cmp; bc; isync Load seq cst hwsync;ld; cmp; bc; isync 1 Using sequential consistency on machines with relaxed memory models makes it easier to write correct parallel code which will be slow. 2 Even if your code is safety critical (when people can die due to bugs) and performance is not an issue, you should not use SC, use a single threaded C program instead. Jonas Skeppstedt (js@cs.lth.se) Lecture 6 2013 58 / 70
Store Store relaxed st Store release lwsync;st Store seq cst hwsync;st 1 It’s easier to program under sequential consistency! 2 Yes, but, why would you want to use synchronization instructions before every store in a critical section since nobody should look at the data before you have left the critical section anyway? 3 Write buffering permitted by store relaxed allows the machine to pipeline all the stores in the critical section. 4 At the end of the critical section you use store release and wait for the remaining preceding stores (now possibly waiting in a write buffer) to complete (i.e. invalidate the other copies if there are any left). Jonas Skeppstedt (js@cs.lth.se) Lecture 6 2013 59 / 70
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Threads in the new ISO C Standard f
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Atomic Objects Atomic objects are n
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Using Atomic Objects Members of an
Page 7 and 8: Lock Free Property To know whether
Page 9 and 10: Memory Order for Atomic Operations
Page 11 and 12: Answer: Yes The code may execute in
Page 13 and 14: Atomic Compare and Exchange There a
Page 15 and 16: Weak Compare and Exchange Functions
Page 17 and 18: Atomic Fetch and Modify Functions T
Page 19 and 20: Atomic Flag The atomic flag type an
Page 21 and 22: The C11 Memory Consistency Model fo
Page 23 and 24: Release and Acquire, and Consume Re
Page 25 and 26: Happens Before and Data Races We wi
Page 27 and 28: Sequenced Before The most common se
Page 29 and 30: An Example _Atomic int m; int u; //
Page 31 and 32: Dependences Dependences are intra-t
Page 33 and 34: Definition of Dependency in C11 A c
Page 35 and 36: Inter-Thread Happens Before An eval
Page 37 and 38: Read-Copy Update RCU is an alternat
Page 39 and 40: A Simplified Example Consider the f
Page 41 and 42: More Details About Dependences Reca
Page 43 and 44: Constant Propagation Example 2(3) T
Page 45 and 46: One More Data Dependency a = atomic
Page 47 and 48: Load and Reserve/Store Conditional
Page 49 and 50: Power Memory Barrier Instructions T
Page 51 and 52: lwsync Memory Barrier for Release O
Page 53 and 54: c;isync Memory Barrier for Load Acq
Page 55 and 56: Cumulative Ordering If the memory a
Page 57: Implementation on Power The followi
Page 61 and 62: Acquire and Release a Spin Lock # a
Page 63 and 64: Initialization Function void call_o
Page 65 and 66: Mutex Options for mtx_init Function
Page 67 and 68: Condition Variable Functions int cn
Page 69 and 70: Thread Functions int thrd_create(th
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Threads in the new ISO C Standard from 2011

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