Threads in the new ISO C Standard from 2011

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isync Memory Barrier The A and B sets consist of all instructions preceding and following the isync, respectively. An instruction which cannot raise an exception in the pipeline can be allowed to complete and instructions following the isync therefore actually execute without order. Consider the sequence: ldw r1,r2,r3 isync stw r4,r5,r6 The store may execute before the load if the load had e.g. a cache miss. This is not what we want and to overcome that problem we can exploit that Power does not permit speculative execution of store instructions. Jonas Skeppstedt (js@cs.lth.se) Lecture 6 2013 52 / 70
c;isync Memory Barrier for Load Acquire By inserting a conditional branch, bc, before the isync both the isync and stw become speculative until the branch outcome is known. We can use beq as follows: ldw r1,r2,r3 # r1 = MEMORY[r2+r3] cmp. r1,r1 # certainly true but the beq must beq # wait according to the specification isync # since no speculative stw is allowed. stw r4,r5,r6 Since the store may not execute speculatively it must wait for the branch outcome. This memory barrier is the fastest. The previous two, however, can order instructions from different processors due to the hwsync/lwsync are cumulative — see below. Jonas Skeppstedt (js@cs.lth.se) Lecture 6 2013 53 / 70
Page 1 and 2: Threads in the new ISO C Standard f
Page 3 and 4: Atomic Objects Atomic objects are n
Page 5 and 6: Using Atomic Objects Members of an
Page 7 and 8: Lock Free Property To know whether
Page 9 and 10: Memory Order for Atomic Operations
Page 11 and 12: Answer: Yes The code may execute in
Page 13 and 14: Atomic Compare and Exchange There a
Page 15 and 16: Weak Compare and Exchange Functions
Page 17 and 18: Atomic Fetch and Modify Functions T
Page 19 and 20: Atomic Flag The atomic flag type an
Page 21 and 22: The C11 Memory Consistency Model fo
Page 23 and 24: Release and Acquire, and Consume Re
Page 25 and 26: Happens Before and Data Races We wi
Page 27 and 28: Sequenced Before The most common se
Page 29 and 30: An Example _Atomic int m; int u; //
Page 31 and 32: Dependences Dependences are intra-t
Page 33 and 34: Definition of Dependency in C11 A c
Page 35 and 36: Inter-Thread Happens Before An eval
Page 37 and 38: Read-Copy Update RCU is an alternat
Page 39 and 40: A Simplified Example Consider the f
Page 41 and 42: More Details About Dependences Reca
Page 43 and 44: Constant Propagation Example 2(3) T
Page 45 and 46: One More Data Dependency a = atomic
Page 47 and 48: Load and Reserve/Store Conditional
Page 49 and 50: Power Memory Barrier Instructions T
Page 51: lwsync Memory Barrier for Release O
Page 55 and 56: Cumulative Ordering If the memory a
Page 57 and 58: Implementation on Power The followi
Page 59 and 60: Store Store relaxed st Store releas
Page 61 and 62: Acquire and Release a Spin Lock # a
Page 63 and 64: Initialization Function void call_o
Page 65 and 66: Mutex Options for mtx_init Function
Page 67 and 68: Condition Variable Functions int cn
Page 69 and 70: Thread Functions int thrd_create(th

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