Threads in the new ISO C Standard from 2011

More documents

Recommendations

Info

Load and Reserve/Store Conditional Behaviour The load instruction fetches data from a memory location, and makes a reservation R in memory. If a different processor modifies the same memory location, the reservation R is lost. If/when the processor with a reservation makes a conditional store, the memory location is modified only if the reservation was not lost in between. Therefore it’s an atomic read-modify-write. The stwcx. conditional store in Power sets a condition code to indicate whether the store succeeded or not (the dot in the mnemonic indicates that the condition code is set by an operation on Power). Jonas Skeppstedt (js@cs.lth.se) Lecture 6 2013 48 / 70
Power Memory Barrier Instructions The Power memory barrier instructions create a memory barrier with two sets of instructions: the A-set with instructions ai preceding the barrier, and the B-set with instructions bj following the barrier. Depending on which barrier instruction is used, some bj instructions may be reordered with some ai instructions. Jonas Skeppstedt (js@cs.lth.se) Lecture 6 2013 49 / 70
Page 1 and 2: Threads in the new ISO C Standard f
Page 3 and 4: Atomic Objects Atomic objects are n
Page 5 and 6: Using Atomic Objects Members of an
Page 7 and 8: Lock Free Property To know whether
Page 9 and 10: Memory Order for Atomic Operations
Page 11 and 12: Answer: Yes The code may execute in
Page 13 and 14: Atomic Compare and Exchange There a
Page 15 and 16: Weak Compare and Exchange Functions
Page 17 and 18: Atomic Fetch and Modify Functions T
Page 19 and 20: Atomic Flag The atomic flag type an
Page 21 and 22: The C11 Memory Consistency Model fo
Page 23 and 24: Release and Acquire, and Consume Re
Page 25 and 26: Happens Before and Data Races We wi
Page 27 and 28: Sequenced Before The most common se
Page 29 and 30: An Example _Atomic int m; int u; //
Page 31 and 32: Dependences Dependences are intra-t
Page 33 and 34: Definition of Dependency in C11 A c
Page 35 and 36: Inter-Thread Happens Before An eval
Page 37 and 38: Read-Copy Update RCU is an alternat
Page 39 and 40: A Simplified Example Consider the f
Page 41 and 42: More Details About Dependences Reca
Page 43 and 44: Constant Propagation Example 2(3) T
Page 45 and 46: One More Data Dependency a = atomic
Page 47: Load and Reserve/Store Conditional
Page 51 and 52: lwsync Memory Barrier for Release O
Page 53 and 54: c;isync Memory Barrier for Load Acq
Page 55 and 56: Cumulative Ordering If the memory a
Page 57 and 58: Implementation on Power The followi
Page 59 and 60: Store Store relaxed st Store releas
Page 61 and 62: Acquire and Release a Spin Lock # a
Page 63 and 64: Initialization Function void call_o
Page 65 and 66: Mutex Options for mtx_init Function
Page 67 and 68: Condition Variable Functions int cn
Page 69 and 70: Thread Functions int thrd_create(th

Threads in the new ISO C Standard from 2011

Create successful ePaper yourself

Delete template?

Save as template?