Laboratory Exercises, C++ Programming
Laboratory Exercises, C++ Programming
Laboratory Exercises, C++ Programming
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14 Tools for Practical <strong>C++</strong> Development<br />
1.3 Rules for Linking<br />
In our example makefile, we used an explicit rule for linking. Actually, there is an implicit rule<br />
for linking, which looks (after some variable expansions) like this:<br />
$(CC) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@<br />
LDFLAGS are options to the linker, such as -Ldirectory. LOADLIBES and LDLIBS 6 are variables<br />
intended to contain libraries, such as -llab1. So this is a good rule, except for one thing: it<br />
uses $(CC) to link, and CC is by default gcc, not g++. But if you change the definition of CC, the<br />
implicit rule works also for <strong>C++</strong>:<br />
# Define the linker<br />
CC = g++<br />
1.4 Generating Prerequisites Automatically<br />
While you’re working with a project the prerequisites are often changed. New #include directives<br />
are added and others are removed. In order for make to have correct information of the<br />
dependencies, the makefile must be modified accordingly. The necessary modifications can be<br />
performed automatically by make itself.<br />
A3. Read the make manual, section 4.14 “Generating Prerequisites Automatically”, and implement<br />
such functionality in your makefile. Hint: Copy the %.d rule (it is not necessary that<br />
you understand everything in it) to your makefile and make suitable modifications. Do not<br />
forget to include the *.d files.<br />
The first time you run make you will get a warning about .d files that don’t exist. This<br />
is normal and not an error. Look at the .d files that are created and see that they contain<br />
the correct dependencies.<br />
One useful make facility that we haven’t mentioned earlier is wildcards: as an example,<br />
you can define the variable SRC as a list of all .cc files with SRC = $(wildcard *.cc). And<br />
from this you can get all .o files with OBJ = $(SRC:.cc=.o).<br />
From now on, you must update the makefile when you add new programs, so that you<br />
can always issue the make command in the build directory to build everything. When you<br />
add a new program, you should only have to add a rule that defines the .o-files that are<br />
necessary to link the program, and maybe add the program name to a list of executables.<br />
This is important — it will save you many hours of command typing.<br />
(Optional) Collect all object files not containing main functions into a library, and link<br />
executables against that library. If you know how to create shared libraries, use a shared<br />
library libcxx.so, otherwise create a static archive libcxx.a.<br />
1.5 Writing a Good Makefile<br />
A makefile should always be written to run in sh (Bourne Shell), not in csh. Do not use special<br />
features from, e.g., bash, zsh, or ksh. The tools used in explicit rules should be accessed through<br />
make variables, so that the user can substitute alternatives to the defaults.<br />
A makefile should also be written so that it doesn’t have to be located in the same directory<br />
as the source code. You can achieve this by defining a SRCDIR variable and make all rules refer<br />
to the source code from that prefix. Even better is to use the variable VPATH, which specifies a<br />
search path for source files. Vpath is described in section 4.5 of the make manual.<br />
6 There doesn’t seem to be any difference between LOADLIBES and LDLIBS — they always appear together and are<br />
concatenated. Use LDLIBS.