Solaris Application Programming, 1/e - Chapter 4 - Parent Directory
Solaris Application Programming, 1/e - Chapter 4 - Parent Directory
Solaris Application Programming, 1/e - Chapter 4 - Parent Directory
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4.2 TOOLS THAT REPORT SYSTEM CONFIGURATION 53<br />
It is also possible to bind a single process to a particular processor using the<br />
pbind command, which takes the -b flag together with the pid and the processor<br />
ID as inputs when binding a process to a processor, and the -u flag together with<br />
the pid to unbind the process. Unlike processor sets that exclude other processes<br />
from running on a given group of processors, processor binding ensures that a particular<br />
process will run on a particular processor, but it does not ensure that other<br />
processes will not also run there.<br />
4.2.5 Reporting Instruction Sets Supported by Hardware (isalist)<br />
isalist is a <strong>Solaris</strong> tool that outputs the instruction sets architectures (ISAs) the<br />
processor supports. This can be useful for picking the appropriate compiler options<br />
(this will be covered in Section 5.6.5 of <strong>Chapter</strong> 5). It is also useful in determining the<br />
particular variant of CPU that the system contains. Example 4.6 shows output from<br />
the isalist command on an UltraSPARC III-based system. It shows that there is a<br />
SPARC processor in the system, and that this can handle SPARC V7, V8, and V9<br />
binaries. The processor can also handle the VIS 2.0 instruction set extensions.<br />
Example 4.6 Sample Output from the isalist Command<br />
$ isalist<br />
sparcv9+vis2 sparcv9+vis sparcv9 sparcv8plus+vis sparcv8plus sparcv8<br />
sparcv8-fsmuld sparcv7 sparc<br />
4.2.6 Reporting TLB Page Sizes Supported by Hardware<br />
(pagesize)<br />
In Section 1.9.2 of <strong>Chapter</strong> 1 we discussed the Translation Lookaside Buffer (TLB),<br />
which the processor uses to map virtual memory addresses to physical memory<br />
addesses. Different processors are able to support different page sizes. The advantage<br />
of larger page sizes is that they let the TLB map more physical memory using<br />
a fixed number of TLB entries. For example, a TLB with 64 entries can map<br />
8KB*64=512KB when each entry is an 8KB page, but can map 4MB*64=256MB<br />
when each entry holds a 4MB page. The number of different page sizes that can be<br />
supported simultaneously is hardware-dependent. Even if the hardware supports<br />
large page sizes, there is no guarantee that an application will recieve large pages<br />
if it requests them. The number of available large pages depends on the amount of<br />
memory in the system and the degree to which contiguous memory is available.<br />
The pagesize command prints out the different TLB page sizes that the processor<br />
can support. If no flags are specified, the utility will print the default page size. If<br />
the flag -a is used, it will report all the available page sizes (see Example 4.7).