Presentation - LLP: Maximizing Performance of Leadframe Packages

LLP: Maximizing Performance
of Leadframe Packages
Neeraj Pendsé
National Semiconductor Corporation
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What Is the LLP? (1 of 2)
• Lead-frame based package,
but no external leads.
• Plastic molded, chip scale
package (CSP)
• Available sizes:
– 3 mm x 3 mm to
11 mm x 11 mm
– 0.6 - 0.8 mm height
• Available lead counts:
8-lead dual up to
128-lead quad
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What is the LLP? (2 of 2)
Mold
Wirebonds
Leads
Board lands
Board
Plane
Vias
DAP
Optimizing the design of the LLP using Ansoft
Spicelink software:
– Power-ground network
– Board grounding schemes
– Leadframe design for specific products
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Package
QFP
Leadframe Package
Comparison
Body size
(mm)
Number
of leads
L (nH) M (nH) C (pF) C M12 (pF)
Corner Center
Corner Center
M12 M13 M12 M13
Corner Center Corner Center
28 · 28 208 12.00 8.00 8.00 6.50 5.50 4.50 0.20 0.06 1.00 0.60
20 · 14 128 4.50 2.40 2.80 2.20 1.40 1.10 0.10 0.05 0.45 0.20
12 · 12 80 2.90 2.40 2.30 1.60 1.30 0.90 0.15 0.10 0.27 0.20
LLP all sizes all 0.01 0.01 0.001 0.001 0.001 0.001 0.03 0.03 0.03 0.03
Mini SOIC 5 x 5 8 0.45 0.45 0.15 0.08 0.15 0.08 0.05 0.05 0.04 0.04
SSOP 5.3 x 10.2 28 2.9 1.3 1.45 0.85 0.6 0.35 0.2 0.08 0.27 0.1
PLCC 11.4 x 11.4 28 4.4 3.2 2 1.5 1.5 1.1 0.35 0.25 0.6 0.45
Wire bond Inductance: Notes:
Length:
L (nH):
0.5
0.32
1
0.78
2
1.83
3
2.99
4
4.22
5
5.5
1. Approximate, typical information
2. Partial AC Inductance
3. Self capacitance with respect to PC
M (nH): 0.2 0.53 1.33 2.23 3.2 4.21
board plane @0.5 mm
4. Wirebond information is separately
provided.
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Reducing Power Inductance
• Up to two power rings can
be incorporated, with
multiple wire bonds.
• Example: for 56 lead LLP:
– Ring 1, wire = 1.5 mm,
5 bonds per side;
L = 0.093 nH.
– Ring 2, wire = 2 mm,
5 bonds per side;
L = 0.125 nH.
– Total loop < 0.2 nH!
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Transient Circuit Simulation
• Comparison of a QFP-32 with an LLP-56:
– 2-GHz, 100-pS rise time differential signals
– Measured crosstalk and power bounce
• LLP: VDD ring and VSS paddle.
• QFP: power leads adjacent to signal leads.
• Package models created with Ansoft Q3D
and simulated on Maxwell SPICE.
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QFP
LLP
Power Bounce and Crosstalk
Power
bounce (V)
Crosstalk (V)
3.40
3.35
3.30
3.25
3.20
0.44
0.42
0.40
0.38
0.36
0 0.5 1 1.5 2
0 0.5 1 1.5 2
Time (nS)
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Is This All True?
• Measurement based co-relation on LLP packages and
other interconnects shows satisfactory agreement with
SPICELINK software
• Some observations:
– Self inductance match is “excellent” (~3%)
– Sometimes hard to get mutual agreement
(~ 10% deviations observed in some cases)
– DC resistance is dead-on (~1%) with lab measurements
– Capacitance agreement is < 5%.
• The process of translation of measurements into partial
inductance may not have a unique solution.
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Why You Should Be Using LLP
Packages
• Small size: height 0.6-mm
• Lower cost than comparable packages
• Better thermal performance
• Uses standard SMT process flow
• Moisture sensitivity level (MSL) 1
• Can accommodate multiple chips
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National’s Packaging
Resources
• LLP packaged parts are currently in full production
(millions of units)
– Wireless, networking, power management …
• Application Note 1205: Electrical Performance of
Packages
• For electrical models of products and packaging,
please contact your local National Semiconductor
sales representative.
• Web site: http://www.national.com
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