E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

14 ICR Interrupt Inputs Clear Reservation
0 External Input and Critical Input Interrupts do not affect reservation status
1 External Input and Critical Input Interrupts clear an outstanding reservation
e200z1 Power Architecture Core Reference Manual, Rev. 0
Register Model
15 NHR Not hardware reset
0 Indicates to a reset exception handler that a reset occurred if software had previously set this bit
1 Indicates to a reset exception handler that no reset occurred if software had previously set this bit
Provided for software use - set anytime by software, cleared by reset.
16 — Reserved 1
17 TBEN TimeBase Enable
0 TimeBase is disabled
1 TimeBase is enabled
18 Reserved Reserved
Table 2-10. Hardware Implementation Dependent Register 0 (continued)
Bits Name Description
19 DCLREE Debug Interrupt Clears MSR[EE]
0 MSR[EE] unaffected by Debug Interrupt
1 MSR[EE] cleared by Debug Interrupt
This bit controls whether Debug interrupts force External Input interrupts to be disabled, or whether
they remain unaffected.
20 DCLRCE Debug Interrupt Clears MSR[CE]
0 MSR[CE] unaffected by Debug Interrupt
1 MSR[CE] cleared by Debug Interrupt
This bit controls whether Debug interrupts force Critical interrupts to be disabled, or whether they
remain unaffected.
21 CICLRDE Critical Interrupt Clears MSR[DE]
0 MSR[DE] unaffected by Critical class interrupt
1 MSR[DE] cleared by Critical class interrupt
This bit controls whether certain Critical interrupts (Critical Input, Watchdog Timer) force Debug
interrupts to be disabled, or whether they remain unaffected. Machine Check interrupts have a
separate control bit.
Note that if Critical Interrupt Debug events are enabled (DBCR0[CIRPT] set (which should only be
done when the Debug APU is enabled), and MSR[DE] is set at the time of a (Critical Input, Watchdog
Timer) Critical interrupt, a debug event is generated after the Critical Interrupt Handler has been
fetched, and the Debug handler is executed first. In this case, DSRR0[DE] is cleared, such that after
returning from the debug handler, the Critical interrupt handler is not run with MSR[DE] enabled.
22 MCCLRDE Machine Check Interrupt Clears MSR[DE]
0 MSR[DE] unaffected by Machine Check interrupt
1 MSR[DE] cleared by Machine Check interrupt
This bit controls whether Machine Check interrupts force Debug interrupts to be disabled, or whether
they remain unaffected.
Note that if Critical Interrupt Debug events are enabled (DBCR0[CIRPT] set (which should only be
done when the Debug APU is enabled), and MSR[DE] is set at the time of a Machine Check
interrupt, a debug event is generated after the Machine Check interrupt handler has been fetched,
and the Debug handler is executed first. In this case, DSRR0[DE] is cleared, such that after
returning from the Debug handler, the Machine Check handler is not run with MSR[DE] enabled.
Freescale Semiconductor 2-19