Audio Codec '97 Revision 2.1

AC ‘97 Component Specification Revision 2.1
D.4 AC ’97 2.1 Power Management
D.4.1 Power Management “D State” Mappings for Audio Codecs
The ACPI and PCI Bus Power Management Interface specifications define a standard set of device power
management states (D0 – D3). An audio device driver written to comprehend these power management
specifications must map each supported system-side D state to an audio Codec-specific power savings mode using
the PR bits.
A high-level set of expectations for the mapping of D States to audio feature availability, power consumption,
resume latency, etc., is available in the Audio Device Class Power Management Reference Specification located at:
http://www.microsoft.com/hwdev/download/audpmspc.rtf
Table 45 details a lower-level mapping of the audio subsystem D states to the recommended AC’97 Codec power
savings PR settings.
PR
90
+12
Vmain
+5Vaa
from
+12
Vmain
+3.3
Vmain
+3.3
Vaux
May 22, 1998
Comments
EAPD HP Int. AC- Mixer Mixer DAC ADC
Amp CLK Link Vref
Device
State
7 6 5 4 3 2 1 0
D0 0 0 0 0 0 0 0 0 On On On On All on
D1 0 0 0 0 0 0 1 1 On On On On -DAC, -ADC
D2 1 0 0 0 0 1 1 1 On On On On -Mix, -Amp
D3hot 1 1 1 0 1/0 1 1 1 On On On On -int clk
Note 3 Note 1 Note 2
-hp amp
D3cold - - - - - - - - Off Off Off On unpowered
Table 45. Recommended Audio Codec D state to PR bit mapping
Note 1: PR4 (AC-link BIT_CLK stopped), is not recommended for D3hot. Under certain circumstances disabling of
the AC-link BIT_CLK during D3hot may interfere with Secondary modem Codec operation, and so is not
recommended. For details on this clocking issue refer to Section D.4.3.5.
Note 2: Disabling of Vref (i.e., PR3 = 1) will impose a hardware-dependent power-up delay upon resuming. An
audio vendor must weigh the incremental power savings that setting PR3 brings, against the added resume latency it
imposes when deciding how the audio driver is to treat this bit while preparing to enter D3hot.
Note 3: The PR5 bit is intended to enable a Primary AC Codec to enter its lowest power internal state while still
providing BIT_CLK to Secondary Codecs on the AC-link. Depending on how PR5 is implemented, AMC or AC +
MC designs may need to manage PR5 identically to PR4.
When the system transitions to a deep sleep state of S3, S4 or S5, all main voltage rails are shut off leaving the audio
Codec unpowered. During each transition to D3hot, the audio driver must assume that it will ultimately end up in
D3cold, and as such, must save off all internal state, and functional context that would be needed to resume correctly
from the D3cold unpowered state.