Audio Codec '97 Revision 2.1

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AC ‘97 Component Specification Revision 2.1 D.3.2 Multi-channel Audio using Multiple Audio Codecs......................................................................... 88 D.3.2.1 Slot to DAC Mappings for Multi-channel Audio Output............................................................................. 88 D.3.2.2 Synchronization for Multi-channel Audio Output ....................................................................................... 89 D.4 AC ’97 2.1 POWER MANAGEMENT......................................................................................................... 90 D.4.1 Power Management “D State” Mappings for Audio Codecs........................................................... 90 D.4.2 Power Management “D State” Mappings for Modem Codecs ........................................................ 91 D.4.3 Power Management with Wake-up Capabilities ............................................................................. 91 D.4.3.1 Clarification of MLNK and AC-link Powerdown ....................................................................................... 91 D.4.3.2 Warm and Cold AC-link Reset Considerations........................................................................................... 93 D.4.3.3 Power Distribution .................................................................................................................................... 96 D.4.3.4 Power Distribution: AMC ’97 (Primary) Implementations ......................................................................... 97 D.4.3.5 Multiple Audio + Modem Codec clocking considerations........................................................................... 97 D.4.4 Resume Latency: Device Driver Considerations............................................................................. 98 D.5 AC ’97 2.1 INTEROPERABILITY REQUIREMENTS AND RECOMMENDATIONS.............................................. 99 D.5.1 Digital SRC in Controller or Codec ............................................................................................... 99 D.5.2 Codec............................................................................................................................................ 99 D.5.2.1 Codec ID .................................................................................................................................................. 99 D.5.2.2 Codec Register Status Reads...................................................................................................................... 99 D.5.2.3 Codec Register Status Read Completion Latency...................................................................................... 100 D.5.2.4 The Codec-Ready Bit and Audio or Modem DAC/ADC Status Bits.......................................................... 100 D.6 AC ’97 2.1 ELECTRICAL CHARACTERISTICS ......................................................................................... 101 D.6.1 3.3 Volt DC Characteristics......................................................................................................... 101 D.6.2 Reset ........................................................................................................................................... 101 D.6.2.1 Cold Reset .............................................................................................................................................. 102 D.6.2.2 Warm Reset ............................................................................................................................................ 102 D.6.3 AC-link Clocks ............................................................................................................................ 103 D.6.4 Data Output and Input Times....................................................................................................... 104 D.6.5 Signal Rise and Fall Times .......................................................................................................... 106 D.6.6 AC-link Low Power Mode Timing................................................................................................ 107 D.6.7 ATE Test Mode............................................................................................................................ 107 D.6.8 AC-link IO Pin Capacitance and Loading .................................................................................... 108 8 May 22, 1998
AC ‘97 Component Specification Revision 2.1 LIST OF FIGURES Figure 1. AC ‘97 1.0 Block Diagram .................................................................................................................. 13 Figure 2. AC ‘97 1.0 System Diagram ................................................................................................................ 14 Figure 3. AC ‘97 48-pin package and pinout....................................................................................................... 18 Figure 4. AC ‘97 48-pin package dimensions...................................................................................................... 18 Figure 5. AC ‘97 64-pin package and pinout....................................................................................................... 20 Figure 6. AC ‘97 64-pin package dimensions...................................................................................................... 20 Figure 7. “Conceptual” example of CD circuit inside of AC ’97......................................................................... 24 Figure 8. Example of vendor-independent external capacitor layout .................................................................... 25 Figure 9. AC ‘97 connection to its companion AC ‘97 Controller........................................................................ 26 Figure 10. AC ‘97 Standard Bi-directional Audio Frame...................................................................................... 28 Figure 11. AC-link Audio Output Frame............................................................................................................. 29 Figure 12. Start of an Audio Output Frame ......................................................................................................... 30 Figure 13. AC-link Audio Input Frame ............................................................................................................... 32 Figure 14. Start of an Audio Input Frame............................................................................................................ 32 Figure 15. AC-link Powerdown Timing.............................................................................................................. 34 Figure 16. AC ‘97 Mixer Functional Diagram..................................................................................................... 36 Figure 17. One example of AC ‘97 Powerdown/Powerup flow............................................................................ 47 Figure 18. AC ‘97 Powerdown/Powerup flow with analog mixer still alive.......................................................... 47 Figure 19. Cold Reset timing diagram.................................................................................................................. 51 Figure 20. Warm Reset timing diagram ................................................................................................................ 51 Figure 21. BIT_CLK to SYNC timing diagram.................................................................................................... 52 Figure 22. Data setup and hold timing diagram .................................................................................................... 53 Figure 23. Signal rise and fall times diagram........................................................................................................ 53 Figure 24. AC-link low power mode timing diagram ............................................................................................ 54 Figure 25. ATE test mode timing diagram ............................................................................................................ 54 Figure 26. Extended AC ’97 2.0 Slot Definitions ................................................................................................. 56 Figure 27. Audio and Modem Slot Assignments .................................................................................................. 65 Figure 28. “Conceptual” Example of GPIO Pin Implementation........................................................................... 71 Figure 29. Combined Audio / Modem AFE Auxiliary Power Distribution ............................................................ 73 Figure 30. AC-link Low Power Mode.................................................................................................................. 73 Figure 31. AC-link Warm Reset .......................................................................................................................... 74 Figure 32. AC-link Power-down/Up Sequence..................................................................................................... 74 Figure 33. Split Partitioned Design Example........................................................................................................ 75 Figure 34. Loopback points .................................................................................................................................. 77 Figure 35. Multiple Codec Example..................................................................................................................... 80 Figure 36. Cold Reset timing diagram................................................................................................................ 102 Figure 37. Warm Reset timing diagram .............................................................................................................. 102 Figure 38. BIT_CLK and SYNC Timing diagram............................................................................................... 103 Figure 39. Data Output and Input Timing Diagram ............................................................................................. 104 Figure 40. Signal Rise and Fall Timing Diagram................................................................................................. 106 Figure 41. AC-link low power mode timing diagram .......................................................................................... 107 Figure 42. ATE test mode timing diagram .......................................................................................................... 107 9 May 22, 1998
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Audio Codec '97 Revision 2.1

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