Audio Codec '97 Revision 2.1
Audio Codec '97 Revision 2.1
Audio Codec '97 Revision 2.1
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AC ‘97 Component Specification <strong>Revision</strong> <strong>2.1</strong><br />
A.3.2 Input Slot 1: Status Address Port / SLOTREQ Bits<br />
<strong>Audio</strong> Input Frame Slot #1, the Status Address Port, now delivers <strong>Codec</strong> control register read address and variable<br />
sample rate slot request flags for all output slots. Ten of the formerly-reserved least significant bits have been<br />
defined as data request flags for output slots 3-12.<br />
Input Slot 1<br />
Bit Description<br />
19 RESERVED (Set to 0)<br />
18-12 Control Register Index (Set to 0s if tagged “invalid” by AC ’97)<br />
11-2 On Demand Data Request Flags (next output frame): 0= send data, 1= do NOT send data<br />
11 Slot 3 request: PCM Left channel<br />
10 Slot 4 request: PCM Right channel<br />
9 Slot 5 request: Modem Line 1<br />
8 Slot 6 request: PCM Center<br />
7 Slot 7 request: PCM Left surround<br />
6 Slot 8 request: PCM Right surround<br />
5 Slot 9 request: PCM LFE<br />
4 Slot 10 request: Modem Line 2 or PCM Left (n+1)<br />
3 Slot 11 request: Handset or PCM Right (n+1)<br />
2 Slot 12 request: PCM Center (n+1)<br />
1,0 RESERVED (Set to 0)<br />
Table 34. Input Slot 1-Bit Definitions<br />
The <strong>Audio</strong> Input Frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY indicates valid<br />
Status Address Port data (Control Register Index). The <strong>Codec</strong> should only set SDATA_IN tag bits for Slot 1<br />
(Address) and Slot 2 (Data) to 1 when returning valid data from a previous register read. They should otherwise be<br />
set to 0. SLOTREQ bits have validity independent of the Slot 1 tag bit.<br />
SLOTREQ bits are always 0 in the following cases<br />
• Non-variable rate <strong>Codec</strong><br />
• fixed rate mode (VRA=0)<br />
• inactive (powered down) DAC channel (VRA=0 or 1)<br />
SLOTREQ bits are only set to 1 by the <strong>Codec</strong> in the following case<br />
• Variable rate audio mode (VRA=1) AND active (power ready) DAC AND a non-48 kHz DAC sample rate and<br />
<strong>Codec</strong> does not need a sample<br />
A.3.3 SLOTREQ Behavior and Power Management<br />
SLOTREQ bits for fixed rate, powered down, and all unsupported Slots should be driven with 0s for maximum<br />
compatibility with the original AC <strong>'97</strong> Component Specification. When a DAC channel is powered down, it<br />
disappears completely from the serial frame: output tag and slot are ignored, and the SLOTREQ bit is absent (forced<br />
to zero). The SLOTREQ bit should be forced to 1 in the interval between when the power-down bit for its<br />
associated channel is turned off and when its channel is ready to accept samples. Controllers can take advantage of<br />
this scheme to eliminate the need to poll the AC ’97, AMC ’97 or MC ’97 status registers.<br />
When the Controller wants to power-down a channel, all it needs to do is:<br />
1. Disable source of DAC samples in Controller<br />
2. Set PR bit for DAC channel in AC97 registers 26h, 2Ah, or 3Eh<br />
When it wants to power up the channel, all it needs to do is:<br />
1. Clear PR bit for DAC channel in AC98 registers 26h, 2Ah, or 3Eh<br />
2. Enable source of DAC samples in Controller<br />
64<br />
May 22, 1998
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