Audio Codec '97 Revision 2.1

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AC ‘97 Component Specification Revision 2.1 5. Digital Interface 5.1 AC-link Digital Serial Interface Protocol AC ‘97 incorporates a 5 pin digital serial interface that links it to the AC ’97 Controller. AC-link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. With a minimum required DAC and ADC resolution of 16-bits, AC ‘97 could also be implemented with 18 or 20-bit DAC/ADC resolution, given the headroom that the AC-link architecture provides. The control and data slots defined by AC ‘97 1.0 include: • SDATA_OUT TAG 1 output slot (0) • SDATA_IN TAG 1 input slot (0) • Control (CMD ADDR & DATA) write port 2 output slots (1,2) • Status (STATUS ADDR & DATA) read port 2 input slots (1,2) • PCM L & R DAC Playback 2 output slots (3,4) • PCM L & R ADC Record 2 input slots (3,4) • Optional Modem Line 1 DAC 1 output slot (5) • Optional Modem Line 1 ADC 1 input slot (5) • Optional Dedicated Microphone ADC 1 input slot (6) The control and data slots defined by AC ‘97 2.0 include: • Optional 6-channel PCM playback 4 output slots (6,7,8,9) • Optional Modem Line 2, handset output 2 output slots (10,11) • Optional Modem Line 2, handset input 2 input slots (10,11) • Optional Modem IO control 1 output slot (12) • Optional Modem IO status 1 input slot (12) SYNC SDATA_OUT SDATA_IN Slot # 0 1 2 3 4 5 6 7 8 9 10 11 12 TAG Codec ID TAG CMD ADDR STATUS ADDR SLOTREQ 3-12 CMD DATA STATUS DATA PCM L PCM L PCM R PCM R LINE 1 DAC LINE 1 ADC 28 PCM CENTER MIC ADC PCM L SURR RSRVD PCM R SURR PCM LFE RSRVD RSRVD Figure 10. AC ‘97 Standard Bi-directional Audio Frame LINE 2 DAC PCM L ( n+1) LINE 2 ADC HSET DAC PCM R (n+1) HSET ADC IO CTRL PCM C (n+1) IO STATUS The AC ‘97 Controller signals synchronization of all AC-link data transactions. AC ‘97 drives the serial bit clock onto AC-link, which the AC ’97 Controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link data, AC ‘97 for outgoing data and AC ’97 Controller for incoming data, samples each serial bit on the falling edges of BIT_CLK. May 22, 1998
AC ‘97 Component Specification Revision 2.1 The AC-link protocol provides for a special 16-bit 6 time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the data, (AC ‘97 for the input stream, AC ’97 Controller for the output stream), to stuff all bit positions with 0’s during that slot’s active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder of the audio frame where SYNC is low is defined as the “Data Phase”. Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that AC ‘97 be implemented as a static design to allow its register contents to remain intact when entering a power savings mode. 5.1.1 AC-link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting AC ‘97’s DAC inputs, and control registers. As briefly mentioned earlier, each audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16-bits which are used for AC-link protocol infrastructure. 5.1.1.1 Slot 0: TAG Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by AC ‘97 indicate which of the corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-link at its fixed 48 kHz audio frame rate 7 . Figure 11 illustrates the time slot based AC-link protocol. (Please note that Bits 1 and 0 of slot 0 tag phase are now used for AC ’97 2.x compliant multi-point Codec addressing as described in AC ’97 2.0 Appendix C). SYNC BIT_CLK SDATA_OUT End of previous Audio Frame Valid Frame 12.288 MHz Tag Phase Data Phase 20.8uS (48 KHz) 81.4 nS slot(1) slot(2) slot(12) "0" "0" "0" Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) 19 29 0 19 0 19 0 19 0 Slot 1 Slot 2 Figure 11. AC-link Audio Output Frame Slot 3 Slot 12 A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, AC ‘97 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 Controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by AC ‘97 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. 6 15-bits defined, with 1 reserved. 7 Control/Status as well as optional extensions of the baseline AC ‘97 specification, such as the modem line Codec, may take advantage of this feature. See AC ’97 2.x Appendices A-D for full description of the standardized variable rate signaling protocols. May 22, 1998
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