H.264 Hardware Encoder in VHDL A tour of the ... - OpenCores
H.264 Hardware Encoder in VHDL A tour of the ... - OpenCores
H.264 Hardware Encoder in VHDL A tour of the ... - OpenCores
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Zexia <strong>H.264</strong> <strong>Hardware</strong> <strong>Encoder</strong> <strong>in</strong> <strong>VHDL</strong><br />
Target hardware<br />
The design has been compiled for <strong>the</strong> follow<strong>in</strong>g devices:<br />
● Xil<strong>in</strong>x Spartan 3 family - (3174 Slices)<br />
● Altera Cyclone III family – (26,754 LEs)<br />
It is likely to compile successfully for most o<strong>the</strong>r FPGA and ASIC technologies.<br />
This encoder is be<strong>in</strong>g built <strong>in</strong>to a commercial application which uses a Spartan 3A 1400 which is<br />
about 4 times <strong>the</strong> size <strong>of</strong> <strong>the</strong> requirement quoted above.<br />
Note that <strong>the</strong> Cyclone III is ra<strong>the</strong>r larger than <strong>the</strong> Spartan 3 due to <strong>the</strong> use <strong>of</strong> small or unlatched<br />
RAM elements <strong>in</strong> <strong>the</strong> design which <strong>the</strong> Spartan can map to distributed RAM but <strong>the</strong> Cyclone needs<br />
to implement <strong>in</strong> discrete logic. A modification to <strong>in</strong>tra4x4 and <strong>in</strong>tra8x8cc components to permit<br />
TOPI to have a two-clock latency ra<strong>the</strong>r than one would permit latched RAM <strong>in</strong> this situation.<br />
Parameters: PP and SP<br />
It is necessary to <strong>in</strong>clude Picture Parameters (PP) and Stream Parameters (SP) to specify <strong>the</strong> details<br />
<strong>of</strong> <strong>the</strong> encoder for <strong>the</strong> decoder to use. These are usually encoded as separate NAL units which can<br />
be transmitted immediately before <strong>the</strong> first NAL unit <strong>of</strong> image stream.<br />
Some recommended Stream Parameters (SP) are:<br />
pr<strong>of</strong>ile_idc 01000010 ( 66)<br />
constra<strong>in</strong>ed_set0_flag 0 ( 0)<br />
constra<strong>in</strong>ed_set1_flag 0 ( 0)<br />
constra<strong>in</strong>ed_set2_flag 0 ( 0)<br />
constra<strong>in</strong>ed_set3_flag 0 ( 0)<br />
reserved_zero_4bits 0000 ( 0)<br />
level_idc 00101000 ( 40)<br />
seq_parameter_set_id 1 ( 0)<br />
log2_max_frame_num_m<strong>in</strong>us4 1 ( 0)<br />
pic_order_cnt_type 011 ( 2)<br />
num_ref_frames 010 ( 1)<br />
gaps_<strong>in</strong>_frame_num_value_allowed_flag 0 ( 0)<br />
pic_width_<strong>in</strong>_mbs_m<strong>in</strong>us1 000010110 ( 21) **<br />
pic_height_<strong>in</strong>_map_units_m<strong>in</strong>us1 000010010 ( 17) **<br />
frame_mbs_only_flag 1 ( 1)<br />
direct_8x8_<strong>in</strong>ference_flag 1 ( 1)<br />
frame_cropp<strong>in</strong>g_flag 0 ( 0)<br />
vui_parameters_present_flag 0 ( 0)<br />
** Replace <strong>the</strong> pic_width and pic_height with appropriate values, <strong>the</strong>se are <strong>in</strong> 16-pixel-units and<br />
thus <strong>the</strong> parameters here encode an image <strong>of</strong> 352x288.<br />
As a NAL, <strong>the</strong>se can be encoded as (hex bytes):<br />
67 42 00 28 DA 05 82 59<br />
Zexia Access Ltd © 2008 3 <strong>of</strong> 6 <strong>H.264</strong> <strong>Hardware</strong> <strong>Encoder</strong>