H.264 Hardware Encoder in VHDL A tour of the ... - OpenCores
H.264 Hardware Encoder in VHDL A tour of the ... - OpenCores
H.264 Hardware Encoder in VHDL A tour of the ... - OpenCores
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Zexia <strong>H.264</strong> <strong>Hardware</strong> <strong>Encoder</strong> <strong>in</strong> <strong>VHDL</strong><br />
RAM<br />
<strong>in</strong>put: YCC pixel values<br />
DC<br />
transform<br />
De-quantise<br />
Inverse Transform<br />
Reconstruction<br />
I-prediction<br />
Core transform<br />
Quantise<br />
DC<br />
transform<br />
Buffer<br />
CAVLC<br />
To<br />
Bytes<br />
Pr<strong>in</strong>cipal components <strong>in</strong> <strong>H.264</strong> encoder<br />
Note that RAM is usually implemented <strong>of</strong>f-chip<br />
P-prediction<br />
Control<br />
&<br />
Tim<strong>in</strong>g<br />
Headers<br />
output: encoded NAL stream<br />
Zexia Access Ltd © 2008 2 <strong>of</strong> 6 <strong>H.264</strong> <strong>Hardware</strong> <strong>Encoder</strong>