Design of LTCC RF Modules for Communication Systems
Design of LTCC RF Modules for Communication Systems
Design of LTCC RF Modules for Communication Systems
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
Presentation #7<br />
<strong>Design</strong> <strong>of</strong> <strong>LTCC</strong> <strong>RF</strong> <strong>Modules</strong> <strong>for</strong><br />
<strong>Communication</strong> <strong>Systems</strong>
Agenda<br />
◗ <strong>LTCC</strong> Overview & Solution<br />
◗ Embedded Passives Modeling & Library<br />
◗ Example1: PAM Module design<br />
◗ Example2: Coupler Module design<br />
◗ Example3: Switch Module design<br />
◗ Summary
<strong>LTCC</strong> Overview & Solution
<strong>LTCC</strong> Background<br />
◗ What is <strong>LTCC</strong> ?<br />
- <strong>LTCC</strong> is a Process Technology which allows <strong>RF</strong> engineers to<br />
create Passive components in the <strong>LTCC</strong> substrate<br />
◗ <strong>LTCC</strong>(Low Temperature Ceramic C<strong>of</strong>ired)<br />
-Silver and Gold metal alloys are printed onto selected layers <strong>of</strong> the<br />
substrate<br />
-Each layer is a ceramic composite with very stable dielectric<br />
properties<br />
-Compliments silicon integration with embedded passives<br />
-Ceramic technology circuit elements such as capacitors resistors &<br />
inductors<br />
-Low-Temperature process allows <strong>for</strong> the use <strong>of</strong> highly conductive<br />
metals(AG,AU)
Buried Capacitor<br />
<strong>LTCC</strong> Module structure<br />
Bare Chip<br />
Chip Capacitor<br />
Internal Electrode<br />
<strong>LTCC</strong><br />
Transistor<br />
Monolitic IC<br />
Surface Electrode<br />
Buried Inductor<br />
Buried Inductor<br />
Resist<br />
or
<strong>LTCC</strong> Manufacturing process
◗ Castellated<br />
◗ -Most recent development<br />
◗ -Best <strong>RF</strong> per<strong>for</strong>mance<br />
◗ -Lowest cost<br />
◗ Clip lead<br />
◗ -Backward Clip lead<br />
◗ -Backward compatible<br />
◗ -Good mechanical strength<br />
◗ -Medium cost<br />
◗ BGA<br />
◗ -Standard footprint<br />
◗ -Good mechanical strength<br />
◗ -Medium cost<br />
Package Styles
Company<br />
Dupont<br />
Ferro<br />
Heraeus<br />
Kyocera<br />
Samsung<br />
Dielectric<br />
constant<br />
7.8<br />
7.5<br />
5.9<br />
5.9<br />
7.68<br />
9.15<br />
5.6~5.7<br />
9.4~9.5<br />
6.3<br />
6.8<br />
<strong>LTCC</strong> Materials<br />
Substrate & Package<br />
Tangent d<br />
0.0063<br />
0.002<br />
-<br />
0.0012<br />
0.0039<br />
0.0027<br />
-<br />
-<br />
Model<br />
951<br />
943<br />
A6M<br />
A6S<br />
CT800<br />
CT2000<br />
GL550<br />
GL660<br />
TCL-6A<br />
TCL-7A<br />
Description<br />
standard tape<br />
low loss tape<br />
Microwave tape<br />
Low loss microwave tape<br />
zero shirink tape<br />
-<br />
-
<strong>LTCC</strong> Considerations<br />
-Vias-<br />
◗ Via sizes<br />
◗ -Via sizes are 150µm, 200µm and 250µm, as punched to the unfired tape.<br />
◗ -Via diameter is recommended to be close to the tape thickness.<br />
◗ -One via diameter on any tape layer recommended.<br />
◗ Catch pads<br />
◗ -A line connection to a via less than 250µm in diameter shall have a round<br />
catch pad 50 µm larger than the via diameter<br />
◗ Via spacing<br />
◗ -Minimum via to via pitch(center to center) within the same tape layer shall<br />
be 2.5 x via diameter.<br />
◗ -Minimum via stagger between tape layers shall be 2 x via diameter.<br />
◗ -Minimum via center to part edge distance shall be 3 x via diameter.
◗ Stacked vias<br />
◗ -Stacking <strong>of</strong> vias is acceptable through any number <strong>of</strong> layers.<br />
◗ -A stacked via connection results in a bump on the part surface. Staggering<br />
<strong>of</strong> vias is recommended ro avoid this.<br />
◗ -A minimum <strong>of</strong> one layer <strong>of</strong> via stagger is recommended <strong>for</strong> hermeticity.<br />
◗ Thermal vias<br />
<strong>LTCC</strong> Considerations<br />
-Vias-<br />
◗ -Recommended thermal via diameter is 200µm <strong>for</strong> tape materials 951-A2<br />
and 951-AX and 150µm <strong>for</strong> 951-AT<br />
◗ -The minimum via pitch (center to center) in a thermal via shall be 3 x via<br />
diameter<br />
◗ -The maximum thermal via array size is 6.5mm length and width<br />
◗ -The minimum thermal via array to part edge clearance shall be 4mm
<strong>LTCC</strong> Considerations<br />
◗ Line width and spacing<br />
-Conductors-<br />
◗ -The minimum conductor line width shall be 200µm(A)<br />
◗ -Maximum line width is 1.5mm with unlimited length.<br />
◗ -The use <strong>of</strong> 90 o lines is recommended <strong>for</strong> the optimum line width control. But<br />
45 o lines are allowed<br />
◗ -The minimum conductors spacing shall be 200µm(B)<br />
◗ -The minimum conductor line spacing to a via catch pad shall be 175 µm(C)<br />
◗ -The minimum conductor line clearance to the substrate edge shall be 380<br />
µm(D). Lead frame pad clearance to the substrate edge shall be 125 µm<br />
◗ -The minimum SMD pad spacing to a via catch pad shall be 200 µm(F)<br />
◗ -The minimum SMD pad spacing to a conductor line shall be 200 µm<br />
◗ -The minimum SMD pad spacing to substrate edge shall be 500 µm(G)
<strong>LTCC</strong> Considerations<br />
-Ground and power planes-<br />
◗ -Ground and power planes shall be a grid pattern <strong>of</strong> less than 50% conductor<br />
coverage.<br />
◗ -The preferred plane uses 250 µm lines and 550 µm spaces.<br />
◗ -The grid pattern <strong>of</strong> planes on adjacent layers should be <strong>of</strong>fset to provide a<br />
uni<strong>for</strong>m substrate thickness.<br />
◗ -Solid conductor areas on the gridded plane can be used locally to improve<br />
<strong>RF</strong> per<strong>for</strong>mance<br />
◗ -The grid plane connection to a via can be improved by using a square catch<br />
pad that shares the current flow to several grid lines(A)<br />
◗ -A minimum <strong>of</strong> 300 µm spacing shall separate the plane pattern and ant feed<br />
through via. 250µm 300µm 550µm<br />
A
◗ Cavities<br />
<strong>LTCC</strong> Considerations<br />
-Cavities-<br />
◗ -Cavities or holes are produced in the unfired state by punching the cavity<br />
windows to the tape sheets be<strong>for</strong>e lamination.<br />
◗ -The cavity walls shall be a minimum <strong>of</strong> 3.0 mm wide(B)<br />
◗ -Via edge to cavity wall clearance shall be a minimum <strong>of</strong> 2.5 x via<br />
diameter(C)<br />
◗ -The cavity bottom conductor to cavity wall clearance shall be 200 µm (D)<br />
◗ -Buried or exposed conductor to cavity wall clearance shall be a minimum <strong>of</strong><br />
250 µm(E)<br />
◗ -Bond shelf minimum width shall be 0.8 mm(F)<br />
F B E<br />
D<br />
C<br />
A
Challenges in <strong>LTCC</strong> <strong>RF</strong> Module design<br />
◗<strong>RF</strong> characterization data is not readily available<br />
◗ For large embedded components(spiral inductor and parallel plate<br />
capacitors), considerable electrical modeling required.<br />
◗ - coupling with ground and between components<br />
◗ Integrated simulation between Circuit modeling and passive<br />
components realization required<br />
◗ - L : length <strong>of</strong> unconventional line and via , C : area <strong>of</strong> arbitrary shape<br />
<strong>of</strong> plates<br />
◗ - May use coupling amongst components to realize circuit components<br />
("intentional" parasitic)
Multi Layer<br />
Technology<br />
Embedded L,C,R libraries<br />
Hybrid IC Multi-layer Substrate<br />
Chip Monolithic Delay Line<br />
Chip RC network<br />
Microwave/mmwave Package<br />
Ans<strong>of</strong>t <strong>LTCC</strong> Solution<br />
-Empowering pr<strong>of</strong>itability-<br />
Material<br />
Technology<br />
Ceramic Material<br />
Thick Film material<br />
Via-hole Forming<br />
3D <strong>RF</strong> Circuit <strong>Design</strong><br />
Microwave measurement<br />
Circuit + EM simulation<br />
Empowering<br />
3D Integrated Circuit Module<br />
<strong>RF</strong>/MW Circuits<br />
Technology<br />
Passive Components:<br />
Coupler, Balun, Combiner, Hybrids etc.<br />
VCO/PLL module, PA module<br />
Antenna Switch Module<br />
Multilayer BPF/Duplexer
3D Planar<br />
Solver :<br />
Pattern layout analysis<br />
Ans<strong>of</strong>t <strong>Design</strong>er TM<br />
Ans<strong>of</strong>t <strong>LTCC</strong> Solution<br />
-Solver on Demand-<br />
Ans<strong>of</strong>t HFSS<br />
System Solver :<br />
<strong>Design</strong> spec./ architecture<br />
Circuit & Layout :<br />
Circuit design,<br />
Required component<br />
parameters fitting<br />
3D Field Solver:<br />
Full Module Field analysis<br />
be<strong>for</strong>e manufacturing<br />
Equivalent Circuit<br />
Extraction :<br />
Component extraction and<br />
library construction
Embedded Passives Modeling<br />
& Library
Embedded passives<br />
•Embedded passives:<br />
- Part <strong>of</strong> a printed circuit board or a substrate using a type <strong>of</strong><br />
material to make resistors, capacitors or inductors.<br />
-The surface area can be reduced by using embedded passives.<br />
-The Cost can be reduced by replacing SMT components.<br />
-Embedded passives reduce the inherent parasitic.
Embedded Passives<br />
HFSS simulation model includes embedded passives in<br />
typical multilayer <strong>LTCC</strong> substrate<br />
HFSS<br />
Embedded Passives : L C R
Typical Properties <strong>for</strong> Embedded<br />
Component<br />
Resistor<br />
Capacitor<br />
Inductor<br />
<strong>RF</strong> Components<br />
Range<br />
1ohm~1Mohm<br />
1pF~100pF<br />
(DC to 3µF/cm 2 )<br />
1nH~40nH<br />
Tolerance<br />
30% embedded<br />
1% trimmed<br />
5% typical<br />
5% typical<br />
Properties<br />
TCR
Embedded Passives Modeling & Library<br />
Physical Model Analysis<br />
3D solver: Ans<strong>of</strong>t HFSS<br />
Planar EM solver: Ans<strong>of</strong>t <strong>Design</strong>er simulation<br />
Auto Parameter extraction: SpiceLink (Q3D)<br />
Equivalent Circuit with nominal<br />
parameters<br />
Ans<strong>of</strong>t <strong>Design</strong>er Circuit simulation<br />
Optimization by S-parameter fitting<br />
Ans<strong>of</strong>t <strong>Design</strong>er Optimetrics<br />
Circuit Parameter<br />
R , L, C, Q, Fr<br />
Add Passives Libraries<br />
Ans<strong>of</strong>t <strong>Design</strong>er User Library
Ans<strong>of</strong>t <strong>Design</strong>er <strong>for</strong> <strong>LTCC</strong> Modeling<br />
-Circuit Circuit + Planar EM Field Simulation- Simulation<br />
Eq. Circuit<br />
Optimization<br />
Auto generation<br />
Auto generation<br />
Auto generation<br />
Circuit Library<br />
Planar EM
Extracted Capacitor Parameters<br />
Parallel-plate structure:<br />
Cp = e 0 e r s<br />
d<br />
Multiple parallel-plate<br />
=> To obtain sufficient capacitance<br />
Area(mm 2 )<br />
: S<br />
0.5<br />
1<br />
2<br />
3<br />
4<br />
5<br />
Fr(GHz)<br />
11.79<br />
9.85<br />
7.93<br />
6.98<br />
6.44<br />
6.11<br />
t : 0.007mm<br />
er =7.8<br />
Rp(O)<br />
0.11<br />
0.14<br />
0.12<br />
0.08<br />
0.08<br />
0.08<br />
0.1mm<br />
Lp(nH)<br />
1.21<br />
1.35<br />
1.45<br />
1.51<br />
1.53<br />
1.57<br />
2GHz<br />
Cp(pF)<br />
2.27<br />
4.17<br />
7.81<br />
12.24<br />
15.95<br />
19.58<br />
Qmax<br />
331.62<br />
332.19<br />
318.03<br />
315.39<br />
275.81<br />
305.59<br />
d : 0.022mm
L : nH<br />
C : pF<br />
R : O<br />
Extracted Capacitor Parameters<br />
20<br />
18<br />
16<br />
14<br />
12<br />
10<br />
8<br />
6<br />
4<br />
2<br />
0<br />
0.5 1 2 3 4 5<br />
S : Area <strong>of</strong> Capacitors (mm 2 )<br />
Cp<br />
Lp<br />
Rp
Embedded Inductors<br />
For manufacturing, the important design consideration is the catch pad<br />
◗ The inner end <strong>of</strong> the catch pad must clear the adjacent conductor by the<br />
design rule spacing<br />
◗ Preferably, the catch pad should occur at the center point <strong>of</strong> the spiral to<br />
give the best possible yield.
Extracted Inductor Parameters<br />
0.4mm<br />
t : 0.007mm<br />
er : 7.8<br />
N <strong>of</strong> Turns<br />
0.5<br />
1<br />
1.5<br />
2<br />
2.5<br />
3<br />
0.4mm<br />
0.1mm<br />
Fr(GHz)<br />
11.65<br />
8.49<br />
5.76<br />
4.19<br />
3.03<br />
2.38<br />
0.1mm<br />
Rs(O)<br />
0.17<br />
0.11<br />
0.30<br />
0.31<br />
0.47<br />
0.54<br />
Ls(nH)<br />
1.59<br />
2.20<br />
3.25<br />
4.70<br />
6.82<br />
9.56<br />
2GHz<br />
Cs(pF)<br />
0.08<br />
0.13<br />
0.20<br />
0.28<br />
0.40<br />
0.47<br />
Qf<br />
130.87<br />
106.72<br />
90.89<br />
73.40<br />
57.60<br />
30.25
L : nH<br />
C : pF<br />
R : O<br />
Extracted Inductor Parameters<br />
10<br />
9<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
1<br />
0<br />
0.5 1 1.5 2 2.5 3<br />
Number <strong>of</strong> Turns<br />
Cs<br />
Ls<br />
Rs
Advantages:<br />
Embedded Resistor<br />
-Size competitive with the chip resistor.<br />
-The range <strong>of</strong> values should be one ohm to one mega ohm.<br />
-Not limited to surface layer mounting.<br />
Challenges:<br />
-Resistor tolerance and sheet resistivity: Both resistivity and thickness tolerances<br />
are goals which have not been met by resistor materials suitable <strong>for</strong> resistivity<br />
required <strong>for</strong> widespread applications.<br />
-Yields: Yield loss per device must be extremely small (~0.00001) because integral<br />
resistors cannot be repaired.
Ink<br />
A<br />
B<br />
C<br />
D<br />
Ohms/Square<br />
28<br />
311<br />
3,481<br />
31,174<br />
Co-Fired Resistors<br />
Miminimum<br />
Dimension<br />
0.030”<br />
0.030”<br />
0.030”<br />
0.030”<br />
Surface Resistors. DuPont 2000<br />
-+/- 30% untrimmed : low cost<br />
-+/- 1% active laser trimed : higher cost<br />
Overlap: minimum 0.005”<br />
Maximum<br />
Dimension<br />
0.200”<br />
0.200”<br />
0.200”<br />
0.200”<br />
Maximum<br />
Ratio<br />
3:1<br />
3:1<br />
3:1<br />
3:1<br />
W: minimum 0.03”<br />
L : minimum 0.03”<br />
Minimum<br />
Ratio<br />
1:3<br />
1:3<br />
1:3<br />
1:3<br />
R= Rs L<br />
W<br />
Aspect Ratio
0.15mm<br />
0.15mm<br />
Extracted Resistor Parameters<br />
W Rs<br />
Reduced equivalent circuit<br />
<strong>for</strong> the embedded resistor<br />
L<br />
0.15mm<br />
0.1mm<br />
W(mm)<br />
2.4<br />
1.6<br />
0.8<br />
0.8<br />
0.8<br />
2.4<br />
1.6<br />
0.8<br />
0.8<br />
0.8<br />
L(mm)<br />
0.8<br />
0.8<br />
0.8<br />
1.6<br />
2.4<br />
0.8<br />
0.8<br />
0.8<br />
1.6<br />
2.4<br />
Rs<br />
(O/square)<br />
28<br />
28<br />
28<br />
28<br />
28<br />
311<br />
311<br />
311<br />
311<br />
311<br />
Li(nH)<br />
1.53<br />
1.46<br />
1.45<br />
0.90<br />
-<br />
-<br />
-<br />
-<br />
-<br />
-<br />
Ri(O)<br />
11<br />
16<br />
30<br />
61<br />
88<br />
98<br />
144<br />
291<br />
517<br />
822<br />
Ci(pF)<br />
-<br />
-<br />
-<br />
-<br />
-<br />
0.41<br />
0.34<br />
0.27<br />
0.30<br />
0.33
<strong>LTCC</strong> <strong>RF</strong> Module <strong>Design</strong> Example:<br />
Power Amplifier
Power Amplifier Module Application<br />
◗ Introduce<br />
◗ Power Amplifier Module is used to transmitter<br />
<strong>for</strong> handset or repeater.<br />
◗ <strong>Design</strong> rule was used power gain matching and<br />
loadpull analysis.
Power Amplifier Specification<br />
◗ Bluetooth PAM :100mW (level C)<br />
◗ SiGe HBT : Gummel Poon<br />
◗ Device: WLE-Q1X8L (Tachyonics)<br />
Unit cell 60 array<br />
◗ Frequency: 2400Mhz ~ 2483MHz<br />
◗ Gain: ~10dB<br />
◗ Output power: 20 dBm<br />
◗ Vcc=3.5V Ic=140mA<br />
◗ Substrate: Si substrate ε r = 9.8
Power Amp <strong>Design</strong> Procedure<br />
◗ Unit cell parameter<br />
◗ Optimize bias network<br />
◗ Power gain circle matching(linear small signal )<br />
◗ <strong>Design</strong> matching network using Smith Tool<br />
◗ Harmonic balance simulation and Load Pull<br />
Analysis method matching<br />
◗ Nyquist stability analysis<br />
◗ Multi-tone HB intermodulation analysis<br />
◗ Conversion lumped component to embedded<br />
passive component
Unit Cell Parameter<br />
◗ Vcc=3.5V, at 50Ohm loadline : Vmax =7V Imax=140mA<br />
◗ -> Ic=70mA, there<strong>for</strong>e Ic <strong>of</strong> unit cell =70/64 = 1.09mA (Class A)<br />
<strong>for</strong> the increase <strong>of</strong> linearity, Ic was changed 2.2 mA.<br />
◗ Collecter feedback bias circuit : Rb= 300KOhm, Rc is omited.<br />
Unit cell bias
Unit Cell Parameter<br />
◗ Using Smith tool is normalized 50 Ohm make a power gain<br />
matching circuit.<br />
◗ 27 dB Power gain matching circuit added.<br />
S-parameter :gain 27 dB<br />
Smith chart
Unit Cell Parameter<br />
◗ From Dynamic loadline :Vmax-Vmin =3.4V , Imax-Imin=5.1mA<br />
◗ Pload (<strong>for</strong>cast)= Vrms*Irms = (Vmax-Vmin*Imax-Imin)/8 =3.4*5.1/8<br />
Dynamic loadline<br />
= 2.16mW = (3.3dBm)<br />
IV-character curve
Unit Cell Parameter<br />
◗ Forecast P1 dB :2.16mW (3.3dBm) -> result :2.36 dBm<br />
◗ Forecast 64 cell array : 2.16mW * 64 =138mW (21.3 dBm)<br />
Tranducer gain @2.4GHz<br />
G1 dB :input –23.5 dBm<br />
Power sweep @2.4GHz<br />
Pout :input –23.5dBm ->2.36 dBm
Optimize Bias Network Using Current Mirror<br />
◗ Collector feedback circuit is sensitive to changes <strong>of</strong> BF(<strong>for</strong>ward<br />
current gain), current mirror circuit should be used to<br />
supplement <strong>for</strong> it.
Optimize Bias Network Using Current Mirror<br />
◗ Power Amp module using Current mirror<br />
◗ Vcc=3.5V , Ic=120mA , Vctrl = 3.5 V Rc= 1Kohm<br />
Next page
Optimize Bias Network Using Current Mirror<br />
◗ Power Amp module inside DW_1X8L_64<br />
◗ 64 unit cell block arrayed
Optimize Bias Network Using Current Mirror<br />
◗ BF variation <strong>of</strong> unit cell into power Amp module.(BF 200~500)<br />
◗ Collector current variation is about 3mA.<br />
only 3mA.
Optimize Bias Network Using Current Mirror<br />
◗ Collector current(Ic) with variation <strong>of</strong> Vctrl voltage and Rc is<br />
as followed.<br />
Rc (0.5kohm ~ 2kohm) V ctrl (2.5V ~ 4V)
Power Gain Circle Matching<br />
◗ Small signal Analysis <strong>for</strong> PAM (freq. 0.3GHz~5GHz ,100MHz<br />
step)<br />
S21:14.5dB@2.4GHz<br />
Gp :28 dB@2.4GHz<br />
K:0.94 B1:1.5 @2.4GHz<br />
Zin:1.61ohm Zout:14.3 @2.4GHz
Power Gain Circle Matching<br />
◗ Power sweep Analysis <strong>for</strong> PAM<br />
◗ Power range : -20dbm ~10dbm 1dbm(step) @2.4Ghz<br />
Transduce gain @2.4GHz<br />
G1 dB 13.7dB : input -5 dBm<br />
Power sweep @2.4GHz<br />
Pout :input 5dBm ->18.77 dBm
Power Gain Circle Matching<br />
◗ Gain matching circuit generation using Smith tool.<br />
◗ Stability K factor is not >1 ,so negative feedback serial inductor<br />
(Le: 0.1nH) attached at Emitter.<br />
Gp :17 dB@2.4GHz<br />
S21:13.4dB@2.4GHz<br />
K = 1<br />
K with variation <strong>of</strong> Le<br />
K, B1@2.4GHz
<strong>Design</strong> Matching Network Using Smith Tool<br />
◗ Input and Output matching circuit was generated by smith tool.<br />
Input matching circuit<br />
Output matching circuit
<strong>Design</strong> Matching Network Using Smith Tool<br />
◗ S-parameter and Input, Output Impedance With matching<br />
circuit<br />
50 Ohm<br />
GP circuit & S11, S22<br />
S-parameter S21:16.98dB, S11 –41dB,<br />
S22: 14.25dB @2.4 GHz<br />
Input Output Impedance
<strong>Design</strong> Matching Network Using Smith Tool<br />
◗ G1 dB and P1dB variation unmatched and matched.<br />
G1 dB changed 13dB -> 16.98dB<br />
-> input -4dBm<br />
Pout is incrased 18.03dBm<br />
-> 19.03dBm
Harmonic Balance Simulation and Loadpull<br />
◗ Loadpull method get the better output about 1~2dB than<br />
power gain matching.<br />
Loadpull turner added<br />
For the Loadpull analysis<br />
harmonic analysis setup is added.<br />
Input power is 5.5 dBm at 2.4GHz
Harmonic Balance Simulation and Loadpull<br />
◗ Using the loadpull turner get the optimum load matching point<br />
and source matching point get the Gamma S plane power gain<br />
circle.(26.5dB)
Harmonic Balance Simulation and Loadpull<br />
◗ Linearity improved <strong>for</strong> the loadpull matching method.<br />
G1 dB is same input -4dBm Output P1 dB is increased 19.03dBm<br />
-> 20.15dBm
Nyquist Stability Analysis<br />
◗ For the stability verification per<strong>for</strong>m the Nyquist criterion:<br />
The circuit will be unstable if the Nyquist plot encircles the origin<br />
in a clockwise direction.
Multi-tone HB Intermodulation Analysis<br />
◗ Tone1 this is 2.4GHz and tone 2 is 2.41GHz.<br />
◗ Input power is –30 dBm.<br />
◗ OIP3 ~= Pout +IMD2/2<br />
2-tone sinusodal source added<br />
IMD2= -44.5 dBc<br />
IP3= 30.37dBm
Conversion <strong>of</strong> Lumped Components to<br />
Embedded Passive Components<br />
◗ Current mirror bias circuit was included into bare chip.<br />
◗ Matching and bias network was implemented on to <strong>LTCC</strong><br />
substrate.<br />
HBT<br />
Bare chip<br />
Input<br />
bias<br />
Bare chip<br />
Pam module<br />
output
<strong>LTCC</strong> <strong>RF</strong> Module <strong>Design</strong> Example:<br />
Directional Coupler
Coupler Module Application<br />
• Introduction<br />
• Derivation <strong>of</strong> lumped equivalent circuit <strong>for</strong><br />
backward directional coupler<br />
• Several lumped coupler circuits<br />
• Simulation and measurement<br />
• Conclusion
Backward conventional coupler<br />
θ<br />
Input Through<br />
Coupling<br />
θ<br />
Self<br />
Mutual<br />
Inductance<br />
Self<br />
Introduction<br />
Isolation<br />
Elimination<br />
<strong>of</strong><br />
Mutual<br />
Inductance<br />
Ce<br />
Co/2<br />
A Novel Equivalent Circuit<br />
Pi-type Structure<br />
Le<br />
Coupling<br />
Lo<br />
Le<br />
Le Le<br />
Ce<br />
Ce Ce<br />
Co/2
Derivation <strong>of</strong> lumped equivalent circuit <strong>for</strong><br />
backward directional coupler<br />
Symmetrical plane<br />
(E/M Wall)<br />
θ<br />
θ<br />
Ce<br />
Symmetrical<br />
Co<br />
plane<br />
(E/M Wall)<br />
Co<br />
Ce<br />
Symmetrical plane<br />
(E/M Wall)<br />
Le<br />
Lo<br />
Lo<br />
Lo Lo<br />
Le<br />
Le Le<br />
Ce<br />
Co<br />
Co<br />
Ce
Case 1. Transversal symmetrical plane magnetic wall<br />
Magnetic/Electric Wall<br />
(Open, Short)<br />
θ<br />
θ<br />
Magnetic<br />
Wall<br />
(open)<br />
Ce<br />
Co<br />
Le<br />
Lo<br />
Magnetic Wall (open)<br />
M/W<br />
or<br />
E/W
Case 1. Transversal symmetrical plane magnetic wall<br />
Longitudinal symmetrical plane<br />
magnetic wall (even-mode)<br />
Z<br />
Z<br />
Z<br />
in<br />
L<br />
in<br />
= Z<br />
=<br />
∞<br />
= −<br />
θ/2<br />
0e<br />
Zoe<br />
jZ<br />
Z<br />
Z<br />
L<br />
0e<br />
0e<br />
+<br />
+<br />
jZ<br />
jZ<br />
θ<br />
cot<br />
2<br />
0e<br />
L<br />
open<br />
θ<br />
tan<br />
2<br />
θ<br />
tan<br />
2<br />
C =<br />
e<br />
Z<br />
Y<br />
ω<br />
in<br />
0e<br />
Ce<br />
=<br />
1<br />
jω<br />
C<br />
θ<br />
tan<br />
2<br />
e<br />
Z<br />
Z<br />
Y<br />
in<br />
L<br />
in<br />
Longitudinal symmetrical plane<br />
electric wall (odd-mode)<br />
= Z<br />
=<br />
0<br />
= −<br />
0e<br />
Zoe<br />
θ/2<br />
jY<br />
Z<br />
Z<br />
0e<br />
L<br />
0e<br />
+<br />
+<br />
jZ<br />
θ<br />
cot<br />
2<br />
jZ<br />
0e<br />
L<br />
short<br />
θ<br />
tan<br />
2<br />
θ<br />
tan<br />
2<br />
L =<br />
e<br />
Ce<br />
ω sin<br />
Z0e<br />
2<br />
e<br />
θ<br />
Le<br />
1<br />
Yin = + jωC<br />
jω<br />
L<br />
e
Case 2. Transversal symmetrical plane electric wall<br />
Magnetic/Electric Wall<br />
(Open, Short)<br />
θ<br />
θ<br />
Electric<br />
Wall<br />
(short)<br />
Ce<br />
Co<br />
Le<br />
Lo<br />
Electric Wall (short)<br />
M/W<br />
or<br />
E/W
Y<br />
Y<br />
Y<br />
in<br />
L<br />
Longitudinal symmetrical plane<br />
magnetic wall (even-mode)<br />
in<br />
Case 2. Transversal symmetrical plane electric wall<br />
= Y<br />
=<br />
=<br />
0<br />
0o<br />
jY<br />
θ/2<br />
Y<br />
Y<br />
0o<br />
Zoo<br />
L<br />
0o<br />
+<br />
+<br />
jY<br />
θ<br />
tan<br />
2<br />
jY<br />
0o<br />
L<br />
θ<br />
tan<br />
2<br />
θ<br />
tan<br />
2<br />
open<br />
Le<br />
Ce+Co Lo<br />
Y in = jω(<br />
Ce<br />
+ Co<br />
)<br />
1<br />
+<br />
j ω ( L + L )<br />
1<br />
Lo =<br />
− L<br />
2<br />
θ<br />
ω ( Ce<br />
+ Co<br />
) −ωY0<br />
o tan<br />
2<br />
e<br />
o<br />
e<br />
Y<br />
Y<br />
Y<br />
in<br />
L<br />
in<br />
Longitudinal symmetrical plane<br />
electric wall (odd-mode)<br />
= Y<br />
=<br />
∞<br />
= −<br />
0o<br />
Zoo<br />
θ/2<br />
Y<br />
Y<br />
jY<br />
L<br />
0o<br />
0o<br />
+<br />
+<br />
jY<br />
jY<br />
0o<br />
θ<br />
cot<br />
2<br />
L<br />
θ<br />
tan<br />
2<br />
θ<br />
tan<br />
2<br />
Y<br />
short<br />
θ<br />
cot<br />
Ce+Co<br />
Le<br />
Y in = jω(<br />
Ce<br />
+ Co<br />
)<br />
+<br />
1<br />
2<br />
jω<br />
0o<br />
Co = − + − 2<br />
ω 2 ω Le<br />
1<br />
Le<br />
C<br />
e
Summary<br />
Ce<br />
Co/2<br />
Le<br />
Lo<br />
Le<br />
Co/2<br />
Ce<br />
Le Le<br />
Ce Ce<br />
Equivalent Circuit <strong>of</strong><br />
Proposed Coupler<br />
e<br />
o<br />
o<br />
e<br />
o<br />
e<br />
e<br />
o<br />
e<br />
e<br />
e<br />
e<br />
o<br />
e<br />
dB<br />
L<br />
Y<br />
C<br />
C<br />
L<br />
C<br />
L<br />
Y<br />
C<br />
Z<br />
L<br />
Y<br />
C<br />
C<br />
C<br />
Z<br />
Z<br />
C<br />
C<br />
Z<br />
Z<br />
dB<br />
C<br />
C<br />
−<br />
−<br />
+<br />
=<br />
⎟<br />
⎟<br />
⎠<br />
⎞<br />
⎜<br />
⎜<br />
⎝<br />
⎛<br />
−<br />
+<br />
=<br />
=<br />
=<br />
+<br />
−<br />
=<br />
−<br />
+<br />
=<br />
−<br />
=<br />
2<br />
tan<br />
)<br />
(<br />
1<br />
1<br />
2<br />
cot<br />
2<br />
1<br />
2<br />
sin<br />
2<br />
1<br />
2<br />
tan<br />
1<br />
1<br />
1<br />
1<br />
1<br />
log<br />
10<br />
0<br />
2<br />
2<br />
0<br />
0<br />
0<br />
0<br />
0<br />
0<br />
0<br />
0<br />
2<br />
10<br />
θ<br />
ω<br />
ω<br />
ω<br />
θ<br />
ω<br />
θ<br />
ω<br />
θ<br />
ω<br />
Coupling<br />
Coefficient
Ce<br />
Co/2<br />
<strong>LTCC</strong> Application<br />
Le<br />
Lo<br />
Le<br />
Le Le<br />
Ce<br />
Ce Ce<br />
Equivalent Circuit <strong>of</strong><br />
Proposed Coupler<br />
Co/2<br />
Center frequency : 2Ghz<br />
C dB (Coupling Coefficent) : 10 dB<br />
Dielectric constant : 7.8<br />
Simulator : Ans<strong>of</strong>t <strong>Design</strong>er<br />
Spicelink V5.0<br />
HFSS V8.5<br />
Size : 3mm×2.4mm×0.5mm<br />
Element values :<br />
Ce : 2.21pF, Le : 1.43nH<br />
Co/2 : 0.53pF, Lo :1.55nH
Circuit Simulation Result using Ans<strong>of</strong>t <strong>Design</strong>er
Chip-type LC design process using Spicelink<br />
Element<br />
Ce(pF)<br />
Le(nH)<br />
Co/2(pF)<br />
Lo (nH)<br />
Suggested Values<br />
(Calculated)<br />
2.21<br />
1.43<br />
0.53<br />
1.55<br />
Applied Values<br />
(Spicelink V5.0)<br />
1.54<br />
1.3723<br />
0.5682<br />
1.6355
<strong>Design</strong>ed chip-type 10dB lumped-element directional<br />
coupler with a multi-layer configuration.
Simulation Result (Ans<strong>of</strong>t <strong>Design</strong>er & HFSS)<br />
10dB Coupler<br />
Comparisons <strong>of</strong> the circuit simulation and EM simulation on the<br />
designed lumped-element directional couplers.
<strong>LTCC</strong> <strong>RF</strong> Module <strong>Design</strong> Example:<br />
Switch Module Application
Switch Module Application<br />
Triple-Band Front End Block Diagram
Dual-band Antenna Switch Module<br />
• <strong>RF</strong> Antenna/Switchplexer module<br />
• Separating the Band <strong>of</strong> Multi-System<br />
• Key Technology<br />
• <strong>LTCC</strong> technology<br />
• MLC(Multi-layer Ceramic) Technology<br />
• Microwave passive component<br />
• design technology<br />
• Microwave integration technology<br />
• Constitution <strong>of</strong> Switchplexer<br />
• Chip, Antenna Transmitting<br />
and receiving<br />
• Hybrid : Improvement <strong>of</strong> radiation<br />
and matching<br />
• Diplexer : Separating the Dual band<br />
• <strong>RF</strong>-Switch : Separating Tx, Rx<br />
• BPF : Harmonic rejection filter<br />
GSM_Tx<br />
GSM_Rx<br />
DCS_Tx<br />
DCS_Rx<br />
Frequency<br />
880~915MHz<br />
925~960MHz<br />
1710~1785MHz<br />
1805~1880MHz<br />
Insertion<br />
Loss<br />
1.0 dB<br />
0.5 dB<br />
1.0 dB<br />
0.75 dB<br />
Return<br />
Loss<br />
27 dB<br />
25 dB<br />
25 dB<br />
25 dB
Diplexer <strong>Design</strong> Theory<br />
◗ Low Pass + High Pass Filter<br />
LPF<br />
LPF cut<strong>of</strong>f freq.<br />
GSM_Tx<br />
GSM_Rx<br />
~ 960MHz<br />
880~ 915MHz<br />
925~ 960MHz<br />
HPF cut<strong>of</strong>f freq.<br />
DCS_Tx<br />
DCS_Rx<br />
HPF<br />
1710MHz~<br />
1710~1785MHz<br />
1805~1880MHz
Low Pass Filter <strong>Design</strong> by Insertion Loss Method<br />
• Prototype lowpass filter design from spec.<br />
Cut<strong>of</strong>f Frequency � 960 MHz<br />
Insertion Loss � 1 dB max<br />
Return Loss � 25 dB min<br />
Termination � In/Out Port Impedance (50 Ohm)<br />
• Impedance scaling<br />
• Frequency trans<strong>for</strong>mation<br />
• Circuit simulation<br />
• Chip-type Low Pass Filter <strong>Design</strong> from Lumped LPF
Prototype Low Pass Filter <strong>Design</strong> from Spec.<br />
Attenuation characteristic equation <strong>of</strong><br />
Chebyshev type filter<br />
1<br />
10<br />
where<br />
cosh<br />
cosh<br />
1<br />
log<br />
10<br />
)<br />
(<br />
and<br />
cos<br />
cos<br />
1<br />
log<br />
10<br />
)<br />
(<br />
10<br />
'<br />
1<br />
'<br />
1<br />
2<br />
10<br />
'<br />
'<br />
1<br />
'<br />
1<br />
2<br />
10<br />
'<br />
'<br />
1<br />
'<br />
'<br />
1<br />
'<br />
−<br />
=<br />
⎪⎭<br />
⎪<br />
⎬<br />
⎫<br />
⎪⎩<br />
⎪<br />
⎨<br />
⎧<br />
⎥<br />
⎦<br />
⎤<br />
⎢<br />
⎣<br />
⎡<br />
⎟<br />
⎟<br />
⎠<br />
⎞<br />
⎜<br />
⎜<br />
⎝<br />
⎛<br />
+<br />
=<br />
⎪⎭<br />
⎪<br />
⎬<br />
⎫<br />
⎪⎩<br />
⎪<br />
⎨<br />
⎧<br />
⎥<br />
⎦<br />
⎤<br />
⎢<br />
⎣<br />
⎡<br />
⎟<br />
⎟<br />
⎠<br />
⎞<br />
⎜<br />
⎜<br />
⎝<br />
⎛<br />
+<br />
=<br />
≥<br />
−<br />
≤<br />
−<br />
Ar<br />
L<br />
A<br />
A<br />
n<br />
L<br />
n<br />
L<br />
ε<br />
ω<br />
ω<br />
ε<br />
ω<br />
ω<br />
ω<br />
ε<br />
ω<br />
ω<br />
ω<br />
ω<br />
ω<br />
⎪<br />
⎭<br />
⎪<br />
⎬<br />
⎫<br />
⎪<br />
⎩<br />
⎪<br />
⎨<br />
⎧<br />
=<br />
⋅<br />
⋅<br />
⋅<br />
=<br />
=<br />
=<br />
=<br />
+<br />
−<br />
−<br />
−<br />
even<br />
odd<br />
g<br />
n<br />
k<br />
g<br />
b<br />
a<br />
a<br />
g<br />
a<br />
g<br />
g<br />
n<br />
k<br />
k<br />
k<br />
k<br />
k<br />
,<br />
)<br />
4<br />
(<br />
coth<br />
,<br />
1<br />
,<br />
,<br />
3<br />
,<br />
2<br />
4<br />
2<br />
1<br />
2<br />
1<br />
1<br />
1<br />
1<br />
1<br />
0<br />
1<br />
β<br />
γ<br />
⎟<br />
⎠<br />
⎞<br />
⎜<br />
⎝<br />
⎛<br />
+<br />
=<br />
⎟<br />
⎠<br />
⎞<br />
⎜<br />
⎝<br />
⎛ −<br />
=<br />
⎟<br />
⎠<br />
⎞<br />
⎜<br />
⎝<br />
⎛<br />
=<br />
⎥<br />
⎦<br />
⎤<br />
⎢<br />
⎣<br />
⎡<br />
⎟<br />
⎠<br />
⎞<br />
⎜<br />
⎝<br />
⎛<br />
=<br />
=<br />
n<br />
k<br />
b<br />
n<br />
k<br />
a<br />
n<br />
L<br />
where<br />
k<br />
k<br />
Ar<br />
c<br />
π<br />
γ<br />
π<br />
β<br />
γ<br />
β<br />
ω<br />
2<br />
2<br />
sin<br />
2<br />
)<br />
1<br />
2<br />
(<br />
sin<br />
2<br />
sinh<br />
37<br />
.<br />
17<br />
coth<br />
ln<br />
1<br />
Prototype low pass filter with<br />
Chebyshev polynomial
Response Characteristics <strong>of</strong> Chebyshev Type Filter<br />
N=3<br />
N=5<br />
N=7<br />
Attenuation<br />
Comparison <strong>of</strong> the frequency characteristic<br />
according to the number <strong>of</strong> ladder network N<br />
1dB<br />
0. 1dB<br />
0.01dB<br />
VSWR<br />
0.01dB<br />
0. 1dB<br />
1dB<br />
Attenuation<br />
Comparison <strong>of</strong> the frequency characteristic<br />
according to the passband ripple
Impedance Scaling & Frequency Trans<strong>for</strong>mation<br />
VS<br />
= 2.<br />
0<br />
[ V]<br />
0<br />
V L<br />
1<br />
1<br />
= V<br />
1+<br />
1<br />
= 1<br />
[ V]<br />
S<br />
ω<br />
+<br />
VL<br />
'<br />
−<br />
1<br />
Imp.<br />
Imp.<br />
Scaling<br />
Scaling<br />
To obtain the same load<br />
ω1'<br />
ω<br />
=<br />
ω<br />
'<br />
1<br />
c<br />
ω<br />
ω'<br />
voltage,<br />
Freq.<br />
Freq.<br />
Mapping<br />
Mapping<br />
Function<br />
Function<br />
' '<br />
ω : ω = ω : ω<br />
:<br />
1 c<br />
VS<br />
= 2.<br />
0[<br />
V]<br />
R<br />
Z + R<br />
[ V]<br />
= VS<br />
1<br />
0<br />
Frequency trans<strong>for</strong>mation<br />
0<br />
Z o<br />
ωc<br />
+<br />
VL<br />
−<br />
function<br />
R<br />
R =<br />
ω<br />
Z0
Port impedance leveling ratio :<br />
Cut<strong>of</strong>f frequency :<br />
1.Resistor<br />
2.Conductance<br />
Low Pass Filter Summary<br />
ω c<br />
R ( n ) × Z<br />
= g0<br />
or g + 1<br />
= g0<br />
or g + 1<br />
G ( n ) ÷ Z<br />
0<br />
0<br />
Z 0<br />
3.Inductance<br />
g<br />
0<br />
∴L<br />
0<br />
: ω<br />
k<br />
'<br />
1<br />
=<br />
'<br />
1<br />
g<br />
k<br />
g<br />
4.Capacitance<br />
g<br />
∴C<br />
: ω<br />
k<br />
=<br />
g<br />
k<br />
g<br />
k<br />
= Z<br />
0<br />
⎛ ω<br />
⎜<br />
⎝ω<br />
= Z<br />
k<br />
0<br />
⎛ ω<br />
⎜<br />
⎝ω<br />
'<br />
1<br />
c<br />
'<br />
1<br />
c<br />
: ω<br />
c<br />
L<br />
⎞<br />
⎟<br />
⎟×<br />
Z<br />
⎠<br />
: ω<br />
c<br />
C<br />
⎞<br />
⎟ ÷ Z<br />
⎠<br />
k<br />
k<br />
0<br />
0
1 1<br />
−ω1<br />
':<br />
ω'<br />
= :<br />
ω ω<br />
1<br />
ω<br />
ω' = − 1'<br />
ω<br />
ω<br />
1<br />
High Pass Filter <strong>Design</strong><br />
(LPF to HPF Frequency trans<strong>for</strong>mation function)<br />
ω' ω1'<br />
= −<br />
ω ω<br />
1<br />
⎛ ⎞<br />
⎜ ω'<br />
⎟ 1 1<br />
jω'<br />
gi<br />
= jgi<br />
⎜−<br />
= − j<br />
ω ⎟<br />
⎜<br />
1<br />
ω ⎟<br />
⎝<br />
ω<br />
1 ⎠ ω g<br />
1<br />
i<br />
LPF<br />
HPF<br />
Low Pass<br />
gi (C)<br />
gi (L)<br />
High Pass<br />
1<br />
( L)<br />
g i<br />
1<br />
( C)<br />
g i
Port impedance leveling ratio :<br />
Cut<strong>of</strong>f frequency :<br />
where<br />
ω<br />
'<br />
1 =<br />
1<br />
1.Resistor<br />
2.Conductance<br />
High Pass Filter Summary<br />
ω c<br />
R ( n ) × Z<br />
= g0<br />
or g + 1<br />
= g0<br />
or g + 1<br />
G ( n ) ÷ Z<br />
0<br />
0<br />
Z 0<br />
3.Inductance<br />
L<br />
4.Capacitance<br />
C<br />
k<br />
k<br />
=<br />
=<br />
1<br />
g<br />
k<br />
1<br />
g<br />
k<br />
⎛ ω<br />
⎜<br />
⎝ω<br />
⎛ ω<br />
⎜<br />
⎝ω<br />
'<br />
1<br />
c<br />
'<br />
1<br />
c<br />
⎞<br />
⎟<br />
⎟×<br />
Z<br />
⎠<br />
⎞<br />
⎟ ÷ Z<br />
⎠<br />
0<br />
0
Prototype Diplexer <strong>Design</strong><br />
GSM/DCS band Diplexer <strong>Design</strong> using introduced Conventional design theory<br />
Tx : GSM Band (~ 960MHz)<br />
Rx : DCS Band (1710MHz ~)
<strong>Design</strong>ed dual-band Diplexer with a multi-layer<br />
configuration.<br />
Dielectric constant : 7.1<br />
Simulator : Ans<strong>of</strong>t <strong>Design</strong>er<br />
Spicelink V5.0<br />
HFSS V8.5<br />
Size : 5.4mm×4.0mm×1.8mm<br />
Tx : GSM Band (~ 960MHz)<br />
Rx : DCS Band (1710MHz ~)
Circuit Simulation Result using Ans<strong>of</strong>t <strong>Design</strong>er
Simulation Result (Ans<strong>of</strong>t <strong>Design</strong>er & HFSS)<br />
• GSM/DCS Diplexer<br />
Comparisons <strong>of</strong> the circuit simulation and EM simulation on the<br />
designed lumped-element directional couplers.
Conclusion<br />
<strong>LTCC</strong> background and design consideration have been reviewed.<br />
<strong>Design</strong> examples were shown <strong>of</strong><br />
<strong>LTCC</strong> PAM module application<br />
<strong>LTCC</strong> coupler design application<br />
<strong>LTCC</strong> switch module design application<br />
The validity <strong>of</strong> proposed applications was verified by applying to<br />
circuit simulator (Ans<strong>of</strong>t <strong>Design</strong>er)<br />
Small-size chip type circuit model can be realized by using<br />
proposed circuits, and Ans<strong>of</strong>t HF/SI product family.
References<br />
Paolo Antognetti and Giuseppe Massobrio, “Semiconductor Device<br />
Modeling with Spice,” McGraw-Hill Book Company, 1988<br />
Steve C. Cripps, “<strong>RF</strong> Power Amplifier <strong>for</strong> Wireless <strong>Communication</strong>s,”<br />
Aertech House, 1999<br />
Lawrence E. Larson, “<strong>RF</strong> and Microwave Circuit <strong>Design</strong> <strong>for</strong> Wireless<br />
<strong>Communication</strong>s,” Artech House, Inc. 1997<br />
George L. Matthaei, Leo Young “Microwave Filters, impedance-matching<br />
networks, and Coupling structures.” Artech House, Inc. 1980<br />
David M. Pozar “Microwave Engineering” Addison-Wesley Publishing<br />
Company. 1993