C:\tst\data_bi.v 1 `timescale 10ns/1ns 2 3 module data_bi(aDATA ...

C:\tst\data_bi.v
1 `timescale 10ns/1ns
2
3 module data_bi(aDATA, bDATA, PIO, aCS, bCS, RnW, CLR, do, aACK, bACK, DRQ, aIRQ, bIRQ, aA1
, bA1);
4
5 inout [7:0] aDATA;
6 inout [7:0] bDATA;
7
8 reg [7:0] buff;
9 reg holdB = 0;
10
11 input PIO;
12 input aCS;
13 input RnW;
14 input do;
15 input aACK;
16 input CLR;
17 input bIRQ;
18 input aA1;
19
20 output DRQ;
21 reg DRQ = 1;
22
23 output bCS;
24 reg bCS = 1;
25
26 output bA1;
27 reg bA1 = 1;
28
29 output aIRQ;
30 reg aIRQ = 1;
31
32 output bACK;
33 reg bACK = 1;
34
35 // READ (do ST)
36 assign #5 aDATA = ((aCS==0 || aACK==0) && RnW==1) ? bDATA : 8'bz;
37
38 // WRITE (z ST)
39 assign bDATA = (holdB) ? buff : 8'bz;
40
41 always @ (negedge aCS or negedge aACK)
42 begin
43 if (!RnW)
44 begin
45 buff

C:\tst\data_bi.v
72 DRQ