Vergleich von Fpga-Architekturen für partitionierte Wavelet ...
Vergleich von Fpga-Architekturen für partitionierte Wavelet ... Vergleich von Fpga-Architekturen für partitionierte Wavelet ...
¢ ¥§¥¥¥ ¥§¥§©© ¢ ¥§ ¥§¥¥§©© ¢ ¥§¥©© ¥§¥§©© ¢ ¥§ ¥§¥§©© ¢ ¥§¥ ¥§¥§©© ¢ ¥§© ¥§¥§©© ¢ ¥§¥ ¥§¥§©© ¢ ¥§ ¥§¥§©© ¢ ¥§© ¥§¥§©© ¢ ¥§ ¥§¥§©© ¢ ¥§ ¥§¥§©© ¢ ¥§¨© ¥§©¥§©© ¢ ¥§ ¥§¥§©© ¢ ¥§ ¥§¥§©© ¢ ¥§© ¥§¥§©© ¢ ¥§ ¥§¥§©© © © ©©©© © ¥§©© §¡©¥¡§ © ¥§©© §¥© ¡¡ © ¡©¡§¡ ©¡¡ ¡§ ©§ © ©©© ©¡ ¥ ¥§ ¥¥©¡ ¡ ©¥© ¥©¡ © ©¡§¥ §¥¡§ ©¥ ©¥¡§ ©¡§¡ § ©¡§© ©¡¡ © ¡§ © ¡ ©¡¡§© . © ©¡©©© ¥¥©§ ©¡ ¡§© ¡¥ ¡ © ¡ ©¡©© ©¥¥© ©¡¡ ¡ In an optimum implementation, the addition logic can be reduced. During the addition of the two products obtained from the look-up tables, the least significant he x digit (4 bits) is always added to z ero. These bits will theref ore not be affected, or contribute a carry into the next column. Engineering an Optimum Solution X [ 7:0 ] [7:4] 8 [3:0] FPGA Features 4 4 LOOK - UP TABLE 0 x k = 0 1 x k = 2k 3 x k = 3k . . 15x k = 15k LOOK - UP TABLE 0 k 2k 3k . . 15k Figure 2: 8-bit Hybrid Multiplier with Optimum Adder Stage The XC4000 FPGA provides an excellent target architecture for this hybrid technique for the following reasons: • The configurable Logic Blocks (CLBs) contain all the logic to perform 2-bit addition including a fast carry propagation to adjacent CLBs. This yields optimum adders of any size with the minimum of design effort. • Any CLB can be used to represent RAM or ROM. In each case, a CLB can be configured for either a 32 x 1-bit, or 16 x 2-bit memory. RAM or ROM of any data width can then be made by combining these small elements, and is ideal for building the look-up tables in the multiplier. Building a Look-up Table In the 8-bit example, the look-up tables must provide 16 results ranging from 0 to 15 times the m ultiplicand value. Such products are up to 12 bits wide (4+8). This requires 6 CLBs to implement as shown in Figure 3. 12 12 8 4 © ©¡§¡ A D D Programming the Table 12 Y = kX ©©©© © ¥ ¥©© 4 4 4 4 4 4 4 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 Figure 3: Forming a 12-bit Wide Look-Up Table Using Six XC4000 CLBs The data content of each CLB memory is a bit-slice across all the required products and is indicated in the 85 (decimal) times table below (see Table 2). It is necessary to pro- gram each memory element with its required pattern. 16 = CLB
£¤ §©¥ ¥ ©©¡© ¡ ¡ © ©¥ ¡ ¡ §©¥¡©©¡¡ © ¥ ©§©¡§¤ © ¡ ©¡¥ © ©¡¥ §§¥¡©¡ ¥¡ ¡© ©© §©¥¡ §§© ¥§© © ¡§ ©¥ ©¥¡ ¡§ ¡ ¥¡§ §©¡©¡¥ ¥¡¡§¡©¡§§©¥¡§ ¥¡¥¡§¡§¡§© © §§©¡© § ¡§ ¡§ ©¥§ ©© ¡© ¥¡ ¡§§ ©¥¥¡§¡§§©¥¡§ ©¡ ¡©©¡§§¥©¥ ¡¡©¥ ©§¡ ¡¡¡¡¡ © §¥¡© ©¡¡¥ ¡© ¡ ¥ ©¡§ § ©§ § §§¡§© © ©¥© §¡ © ¥¡ ¡¡¡¡§¥ ¥¡ §¡¡ ¡¡¡ © § ¡ ©¡ ©¡§ © ©© ¥¡ §§©¥¡©¥© ¥© ©¥¡§ © ¡§ § ©¥¡¥ ©¡ ¡§¥ §©¥¡ ¡ ¡§©¡¥©©¡ ¡§ ¥©©¡§¡¡© ©© §§©¥¡ ¥¡§ ¥¥©¡ ¡ ¡ §§ ©© © ©¡¡¡¡ ¡ ¥ §©© ¡ ¥¥¡ ©¥ §©¥¡ © © ¥¡§ ©¡ ¡§¡¥ §¡ ¡¥©¡ ¡© ©© §©¥¡© ©¥¡§©©¡§©© ¥ ¡ ¡§¡ ©¡ ¨§ © § ¥¥ ¥ § ¥¡¥ ©¥¡ ©¥¡§¡ ©©¡¡§¥¡©§ ©¥©¥¡ ©©§ §¥¡§ © ©¡ ©§ ¡ §¡ § ¥ © ©¥¡ ©¥¡¥ §¥ © ¡§ ¡© ¡ ¡ §§¥¡ ¡¡©¡ §© § §©¥¡ §¡¡§ ¥¡§ ¡ ¡© ©© §©¥¡§
- Page 13 and 14: ¨¦¨ ¦§¦¦¨ ¨ ¨ ¨ ¨§¨
- Page 15 and 16: ¨¨¨¨¥ ¨ ¨ ¨¨ ¨¨¨
- Page 17 and 18: Eingabesignal j+1 j+1 j+1 j+1 j+1 j
- Page 19 and 20: n Daten {a} Level 1 {a} Level 2 -1
- Page 21 and 22: ¨¥¨¨£¨ ¡ ¡ ¦¡
- Page 23 and 24: ¨¨¨¨¨¨¨¨ ¨¨¨ ¨¨ ¨¨
- Page 25 and 26: © ¨ ¨¨¨ ¥ ¨ ¨¨
- Page 27 and 28: © Rand ohne Teilbilder zusätzli
- Page 29 and 30: ¨
- Page 31 and 32: ¥¢ ¥ ¥
- Page 33 and 34: ¥¢ £ §
- Page 35 and 36: ¥¢ ¨
- Page 37 and 38: ©¥¤¢ £¢ §¦¦ £
- Page 39 and 40: ¡ ¢¥ ¢ §¦§¦
- Page 41 and 42: D A r/w ready ¡ ¢¥ ¢ §¦§¦
- Page 43 and 44: ¡ ¢ §¦§¦ ¨
- Page 45 and 46: ¡ ¢ ¡©¢¥ §¦§¦ ¨¨
- Page 47 and 48: ¢¢¢ ¢
- Page 49 and 50: LL ¦¦¢¤¢ ¢¢¢ £¢ o o o FB
- Page 51 and 52: £ ¡ ¡ ¡ ¡ ¡¡ ¡¡
- Page 53 and 54: £ ¡¡¡ ¡ ¡¡ ¢ ¡¡
- Page 55 and 56: ¡ ¢¤£¦¥¨§©§¥¥ ¡¡
- Page 57 and 58: ©£ § 4 C1 • • • C4 H1 DI
- Page 59 and 60: ©£ XC4000E and XC4000X Series F
- Page 61 and 62: ©£ ¤ ¡
- Page 63: ©¡ ¦ © ©¨ ¢¦¦ §¦ ©
- Page 67 and 68: ¡ ¥ ¡ ©¥¡¡ ¥¡§¥§
- Page 69 and 70: ¨¨ ¨ ¨
- Page 71 and 72: §©¥¡ ©¥ ¥ ¥¥ ¥¡ §
- Page 73 and 74: AW[7:0] WE[3:0] DI[31:0] WE[3] WE[2
- Page 75 and 76: ¡¥¡§ ¡¥ ¥¡©§¡ ¥ ¡
- Page 77 and 78: ¥¥ ¥¡¥¡ ¥ §
- Page 79 and 80: ¥ ¨¨ ¨ § £
- Page 81 and 82: x i x x x i-1 i-2 i-K Summe ¥
- Page 83: ¥§ © ¥
- Page 86: §©¨¨¨ ¡¥¥ © ¥
¢ ¥§¥¥¥ ¥§¥§©© ¢ ¥§<br />
¥§¥¥§©©<br />
¢ ¥§¥©© ¥§¥§©© ¢ ¥§<br />
¥§¥§©©<br />
¢ ¥§¥ ¥§¥§©© ¢ ¥§©<br />
¥§¥§©©<br />
¢ ¥§¥ ¥§¥§©© ¢ ¥§<br />
¥§¥§©©<br />
¢ ¥§© ¥§¥§©© ¢ ¥§<br />
¥§¥§©©<br />
¢ ¥§ ¥§¥§©© ¢ ¥§¨©<br />
¥§©¥§©©<br />
¢ ¥§ ¥§¥§©© ¢ ¥§<br />
¥§¥§©©<br />
¢ ¥§© ¥§¥§©© ¢ ¥§<br />
¥§¥§©©<br />
<br />
© © ©©©© © ¥§©©<br />
<br />
§¡©¥¡§<br />
<br />
© ¥§©© §¥©<br />
¡¡<br />
© ¡©¡§¡ ©¡¡<br />
¡§<br />
©§ © <br />
<br />
©©© ©¡ ¥ ¥§<br />
<br />
<br />
<br />
¥¥©¡ ¡ ©¥© ¥©¡ © ©¡§¥<br />
<br />
§¥¡§ ©¥<br />
<br />
©¥¡§<br />
<br />
<br />
©¡§¡ § ©¡§© ©¡¡ ©<br />
¡§<br />
© ¡<br />
<br />
©¡¡§©<br />
.<br />
<br />
© <br />
©¡©©©<br />
<br />
¥¥©§ ©¡<br />
<br />
¡§© ¡¥ ¡ © ¡<br />
©¡©©<br />
<br />
©¥¥© ©¡¡ ¡ <br />
In an optimum implementation, the addition logic can be<br />
reduced. During the addition of the two products<br />
<br />
obtained<br />
from the look-up tables,<br />
the least significant he x digit (4<br />
bits) is always<br />
added to z ero. These bits will theref ore not<br />
be affected,<br />
or contribute a carry into the next column.<br />
Engineering an Optimum<br />
Solution<br />
<br />
X [ 7:0 ]<br />
<br />
[7:4]<br />
8<br />
[3:0]<br />
FPGA Features<br />
4<br />
4<br />
LOOK - UP <br />
TABLE<br />
0 x k = 0<br />
1 x k = 2k<br />
3 x k = 3k<br />
.<br />
.<br />
15x k = 15k<br />
LOOK - UP TABLE<br />
0<br />
k<br />
2k<br />
3k<br />
.<br />
.<br />
15k<br />
Figure 2: 8-bit Hybrid Multiplier with Optimum<br />
Adder Stage<br />
The XC4000 FPGA provides an excellent target architecture<br />
for<br />
this hybrid technique for the following reasons:<br />
• The configurable Logic Blocks (CLBs) contain all the<br />
logic to perform<br />
2-bit addition including a fast carry<br />
propagation to adjacent CLBs.<br />
This yields optimum<br />
adders of any<br />
size with the minimum of design effort.<br />
• Any CLB can be used to represent RAM or ROM. In<br />
each case,<br />
a CLB can be configured for either a<br />
32 x 1-bit, or 16 x 2-bit memory. RAM or ROM of any<br />
data width can then be made by<br />
combining these small<br />
elements,<br />
and is ideal for building the look-up tables in<br />
the multiplier.<br />
Building a Look-up Table<br />
In the 8-bit example, the look-up tables must provide 16<br />
results ranging<br />
from 0 to 15 times the m ultiplicand value.<br />
Such products are up to 12 bits wide (4+8). This requires 6<br />
CLBs to implement as shown<br />
in Figure 3.<br />
12<br />
12<br />
8<br />
4<br />
<br />
© ©¡§¡<br />
A<br />
D<br />
D<br />
Programming the Table<br />
12<br />
Y = kX<br />
©©©© © ¥ ¥©© <br />
4<br />
4<br />
4<br />
4<br />
4<br />
4<br />
<br />
4<br />
p11<br />
p10<br />
p9<br />
p8<br />
p7<br />
p6<br />
p5<br />
p4<br />
p3<br />
p2<br />
p1<br />
p0<br />
Figure 3: Forming a 12-bit Wide Look-Up Table Using<br />
Six XC4000 <br />
CLBs<br />
The data content of each CLB memory is a bit-slice across<br />
all the required products and is indicated in the 85 (decimal)<br />
times table below (see Table 2). It is necessary<br />
to pro-<br />
gram each memory element with its required pattern.<br />
16<br />
= CLB