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A i+1
B i+1
A i
B i
C i
CARRY LOGIC
Figure 2: Conceptual Diagram of a Typical Addition (2 Bits/CLB)
If only one adder bit is to be implemented per CLB, the
selected carry
may be forced to skip the first stage of carry
logic. To do this, a configuration bit is set to one and
selected to replace the output of the compar
ator. If the bit is
selected and set to zero,
an initial v alue is f orced into the
carry
chain.
This initial v T
alue has three sources, determined by the SUMcon
figuration
bits. The first source is the configuration bit used
to gate out the B operand.
When this bit is a one, a 2-operand
function is performed,
and a one at the carry input pro-
vides add-with-carry
or subtr
act-without-borrow A (borrow T is
active
Low). When the N-1, BN-1
BYP
bit is a zero, a 1-operand function is
performed,
and the carry chain is initialized A
N-2, BN-2
with a zero.
The second source is F3.
If F3 is not selected as the add/
subtract
control, it is a free input to the carr y chain. If it is
used to control addition and subtraction, it A provides a zero T
N-3, BN-3
BYP
or one such that the initial carry
/borrow is un-asser ted in
both cases.
AN-4, BN-4 The final source is F1. When initialization is selected, this is
a free input to the carry
chain.
The second stage of the carry
logic may also be skipped, in
the same way
as the first stage. However, there is no initialization
function in the second stage.
A3, B3 G FNGEN
F FNGEN
B 1
A 1,
B 0
A 0,
CARRY IN (OPTIONAL)
T INCY
T BYP
Figure 3: Carry Propagation Paths
C i+2
S i+1
S i
X1998A
CLB CLB CLB CLB
CARRY OUT (OPTIONAL)
OVERFLOW (OPTIONAL)
SN-1 CLB
S
N-2
CLB
T
CLB
CLB
CLB
CLB
CLB
CLB
SUM
SN-3
AN-2,
BN-2
CLB
SN-4
CLB CLB AN-3, BN-3CLB S3 S1 S0 N-4 CLBs
2
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B N-1
A N-1,
A2,
B2
TBYP S2
A1,
B1
T
XAPP 013 July 4, 1996 (Version 2.0) OPCY
TOPCY A0, B0 3
B 2
A 2,
CARRY IN (OPTIONAL)
¡
X1999A
Figure 2: Alternative Adder Organization
T SUM
T INCY
T BYP
T BYP
TBYP CARRY OUT
(OPTIONAL)
OVERFLOW
(OPTIONAL)
SN-1 S
N-2
SN-3 S2 S1 S0 TSUM N-2
2 CLBs
X1806